tag: TCAD

From Feature-Scale Simulation To Digital Twins: Helping Process Engineers Tackle Growing Complexity
By Saurabh Suryavanshi - 16 Jul, 2026 - Comments: 0

For process engineers facing rising manufacturing complexity, physics-based simulation provides the foundation for understanding what is happening on the wafer. AI, automation, and digital twins become powerful only when they build on that foundation, enabling faster exploration without losing trust, calibration, or engineering judgment. The growing challenge of semiconductor manufacturing Se... » read more

3nm GAA-FET SRAM Review Evaluates Self-Heating And Radiation Hardness (SJSU, Sandia)
By Technical Paper Link - 12 Jul, 2026 - Comments: 0

Researchers from San Jose State University and Sandia National Laboratories published a technical paper titled “Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques.” Abstract Excerpt: “In addition to the traditional bottom dielectric isolation (BDI), which isolates the source/drain (S/D) from the substrate (dubbed SD-BDI),... » read more

Automate And Speed Up TCAD Calibration With Expert Modules And ML Calibration Accelerator
By Saurabh Suryavanshi - 16 Apr, 2026 - Comments: 0

Increasing complexity in semiconductor manufacturing has pushed the time to market and R&D costs significantly higher. In the world of AI, there is increased focus on efficiency to help address these issues simultaneously. Wafer-based learning, which is an iterative and linear process, is a key contributor to the increased semiconductor development time and cost. Technology computer-aided d... » read more

Simulations of Silicon Spin Qubits Based on a GAAFET (Teikyo U., Riken)
By Technical Paper Link - 30 Mar, 2026 - Comments: 0

A new technical paper, "Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor," was published by Teikyo University and RIKEN. Abstract "We theoretically investigated the readout process of a spin–qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configuration... » read more

Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance
By PDF Solutions - 10 Feb, 2026 - Comments: 0

Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. The presented study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7nm FinFET transistors. Variations in critical dimension ... » read more

On-Current Performance of Ultra-Scaled NSFETs With Source/Drain Underlap Doping (Global TCAD Solutions, TU Wien)
By Technical Paper Link - 24 Nov, 2025 - Comments: 0

A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. Abstract: "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solutio... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets
By Shela Aboud - 20 Nov, 2025 - Comments: 0

When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)
By Technical Paper Link - 28 Jun, 2025 - Comments: 0

A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity
By PDF Solutions - 10 Jun, 2025 - Comments: 0

Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

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