Improving ML-Based Device Modeling Using Variational Autoencoder Techniques

A technical paper titled “Improving Semiconductor Device Modeling for Electronic Design Automation by Machine Learning Techniques” was published by researchers at Commonwealth Scientific and Industrial Research Organisation (CSIRO), Peking University, National University of Singapore, and University of New South Wales. Abstract: "The semiconductors industry benefits greatly from the integ... » read more

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National University of Transportation, Samsung Electronics, and Sungkyunkwan University. Abstract: "The high data throughput and high energy efficiency required recently are increasingly difficult to implement... » read more

Challenges In Ramping New Manufacturing Processes

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

What Designers Need To Know About GAA

While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

Artificial Neural Network (ANN)-Based Model To Evaluate The Characteristics of A Nanosheet FET (NSFET)

This new technical paper titled "Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors" was published by researchers at SungKyunKwan University, Korea. Abstract: "In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generat... » read more

TCAD-Based Radiation Modeling Technique For Reliable Aerospace Chips

By Ian Land and Ricardo Borges We demand a lot from the electronic components that bring our devices and systems to life. This is particularly true when it comes to semiconductors for space applications. From satellites to spacecraft, aerospace and defense equipment must tolerate the most extreme of operating conditions in order to perform their jobs safely and reliably. How do you ensure... » read more

Improving Machine Learning-Based Modeling of Semiconductor Devices by Data Self-Augmentation

Abstract: "In the electronics industry, introducing Machine Learning (ML)-based techniques can enhance Technology Computer-Aided Design (TCAD) methods. However, the performance of ML models is highly dependent on their training datasets. Particularly in the semiconductor industry, given the fact that the fabrication process of semiconductor devices is complicated and expensive, it is of grea... » read more

Dynamic in-chip current distribution simulation technology for power device layout design

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification

Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

A New Vision For Memory Chip Design And Verification

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

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