Read-Centric DTCO for IGZO FeFETs 3D Heterogeneous AI memories (imec, KU Leuven)


Researchers from imec and KU Leuven have published “DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective”. Abstract excerpt “This work evaluates the viability of NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) RAMs an... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets


When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

Performance Of A Memory System With FeRAM vs. DRAM (Georgia Tech, Imec, NTUA)


A new technical paper titled "Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model" was published by researchers at Georgia Tech, imec and National Technical University of Athens. Abstract "We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FE... » read more

Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)


A new technical paper titled "Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling" was published by researchers from University of Texas at Austin and Intel. Abstract "Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area ... » read more

Cross-Node Scaling Potential of SOT-MRAM for Last-Level Caches (imec)


A new technical paper titled "SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study" was published by researchers at imec, Leuven, and 3001 Belgium. Abstract "This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate th... » read more

Device Architecture For 2D Material-Based mNS-FETs In Sub-1nm Nodes (Sungkyunkwan Univ., Alsemy)


A new technical paper titled "Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes" was published by researchers at Sungkyunkwan University and Alsemy Inc. "This paper explores the design and optimization of multi-Nanosheet Field-Effect Transistors (mNS-FETs) employing a Transition Metal Dichalcogenide (TMDC) channel, specifically MoS2, for the 0.7 nm technology node u... » read more

TCAD For GPUs And GPUs For TCAD


It is well known that many steps in chip development become exponentially harder as feature sizes shrink and instance counts balloon. Billions of transistors are now commonplace, and wafer-scale devices with trillions are on the horizon. Such massive chips put pressure on every electronic design automation (EDA) tool in the development flow, from front-end architectural modeling to signoff and ... » read more

TCAD-Based AI Models For Modern Fab Workflows


The relentless pace of semiconductor development continues unabated. Despite the slowdown in Moore’s law, feature sizes continue to shrink as new geometries come online. Constant innovations in both fab processes and device design offer new opportunities but present new challenges. As in so many other areas of electronics, artificial intelligence (AI) is starting to play a significant role. ... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)


A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)


A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

← Older posts