tag: DTCO

What Is TCAD And Why It Is Essential For The Semiconductor Industry
By Shela Aboud - 16 Nov, 2023 - Comments: 0

Modern technology computer-aided design (TCAD) technologies have been around now for years. Yet, many semiconductor engineers still run experiments directly on wafers to examine chip fabrication processes and device operation. While it can be challenging to become proficient in TCAD, conducting experiments on wafers isn’t exactly easy, nor is it quick or cost-effective to do. As with so ma... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Challenges In Ramping New Manufacturing Processes
By Ed Sperling - 30 Aug, 2023 - Comments: 0

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Changes In Memory Design
By Ed Sperling - 29 Jun, 2023 - Comments: 0

An explosion of data in automotive, cloud, and AI are altering the fundamentals of memory design. One size no longer fits all, as memory is used for a broader set of applications, from automotive and cloud to consumer devices. Anand Theruvengadam, director of product management at Synopsys, talks about the impact of big data applications on density, memory stacking, and growing concerns about r... » read more

IEDM: Backside Power Delivery
By Paul McLellan - 09 Mar, 2023 - Comments: 0

One part of the short course that I attended at IEDM in December was about backside power delivery networks. It was presented by Gaspard Hiblot of imec and titled "Process Architectures Changes to Improve Power Delivery." The presentation is co-credited with Geert Hellings and Julien Ryckaert. I should preface this post with the fact that this presentation was 80 slides long and so I will only... » read more

Challenges In Backside Power Delivery
By Laura Peters - 17 Nov, 2022 - Comments: 0

One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions. Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on t... » read more

Beyond 5nm: Review of Buried Power Rails & Back-Side Power
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

A new technical paper titled "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes" is presented by researchers at UT Austin, Arm Research, and imec. Find the technical paper here. Published July 2022. S. S. T. Nibhanupudi et al., "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes," in IEEE Transactions... » read more

Distilling The Essence Of Four DAC Keynotes
By Brian Bailey - 28 Jul, 2022 - Comments: 0

Chip design and verification are facing a growing number of challenges. How they will be solved — particularly with the addition of machine learning — is a major question for the EDA industry, and it was a common theme among four keynote speakers at this month's Design Automation Conference. DAC has returned as a live event, and this year's keynotes involved the leaders of a systems comp... » read more

Memory Evolution Drives Requirements For Design Technology Co-Optimization
By Ricardo Borges - 15 Jul, 2022 - Comments: 0

By Ricardo Borges and Anand Thiruvengadam As new technology nodes have become available, memory has been one of the most aggressive semiconductor applications to adopt advanced process technology. The relentless demand by users of electronic devices for more memory has ensured that investments in new nodes and processes would be quickly repaid by massive sales volumes. As each new node came ... » read more

New End Markets, More Demand For Complex Chips
By Ed Sperling - 16 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss economic conditions and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front... » read more

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