tag: DTCO

TCAD For GPUs And GPUs For TCAD
By Shela Aboud - 17 Apr, 2025 - Comments: 0

It is well known that many steps in chip development become exponentially harder as feature sizes shrink and instance counts balloon. Billions of transistors are now commonplace, and wafer-scale devices with trillions are on the horizon. Such massive chips put pressure on every electronic design automation (EDA) tool in the development flow, from front-end architectural modeling to signoff and ... » read more

TCAD-Based AI Models For Modern Fab Workflows
By Saurabh Suryavanshi - 20 Mar, 2025 - Comments: 0

The relentless pace of semiconductor development continues unabated. Despite the slowdown in Moore’s law, feature sizes continue to shrink as new geometries come online. Constant innovations in both fab processes and device design offer new opportunities but present new challenges. As in so many other areas of electronics, artificial intelligence (AI) is starting to play a significant role. ... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

Improving Power and Speed in GAA-NS FETs
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A new technical paper titled "Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling" was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions. Abstract: "Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around ... » read more

3D Device With BEOL-Compatible Channel And Physical Design for Efficient Double-Side Routing
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation, and Carnegie Mellon University. Abstract "This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves ... » read more

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Extending Design Technology Co-Optimization From Technology Launch To HVM With Calibre Fab Solutions
By Siemens EDA - 21 Dec, 2023 - Comments: 0

As IC designs get larger and manufacturing processes get more complex, the semiconductor industry finds itself needing new solutions to prevent the propagation of systematic defects, streamline product cycle time and deliver high-quality, reliable chips. Traditionally, engineers have improved performance, power efficiency, density and cost through design-technology co-optimization (DTCO) techni... » read more

Extending DTCO For Today’s Competitive IC Landscape
By Le Hong - 21 Dec, 2023 - Comments: 0

As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. Designers need to accelerate d... » read more

What Is TCAD And Why It Is Essential For The Semiconductor Industry
By Shela Aboud - 16 Nov, 2023 - Comments: 0

Modern technology computer-aided design (TCAD) technologies have been around now for years. Yet, many semiconductor engineers still run experiments directly on wafers to examine chip fabrication processes and device operation. While it can be challenging to become proficient in TCAD, conducting experiments on wafers isn’t exactly easy, nor is it quick or cost-effective to do. As with so ma... » read more

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