tag: DTCO

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Extending Design Technology Co-Optimization From Technology Launch To HVM With Calibre Fab Solutions
By Siemens EDA - 21 Dec, 2023 - Comments: 0

As IC designs get larger and manufacturing processes get more complex, the semiconductor industry finds itself needing new solutions to prevent the propagation of systematic defects, streamline product cycle time and deliver high-quality, reliable chips. Traditionally, engineers have improved performance, power efficiency, density and cost through design-technology co-optimization (DTCO) techni... » read more

Extending DTCO For Today’s Competitive IC Landscape
By Le Hong - 21 Dec, 2023 - Comments: 0

As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. Designers need to accelerate d... » read more

What Is TCAD And Why It Is Essential For The Semiconductor Industry
By Shela Aboud - 16 Nov, 2023 - Comments: 0

Modern technology computer-aided design (TCAD) technologies have been around now for years. Yet, many semiconductor engineers still run experiments directly on wafers to examine chip fabrication processes and device operation. While it can be challenging to become proficient in TCAD, conducting experiments on wafers isn’t exactly easy, nor is it quick or cost-effective to do. As with so ma... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Challenges In Ramping New Manufacturing Processes
By Ed Sperling - 30 Aug, 2023 - Comments: 0

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Changes In Memory Design
By Ed Sperling - 29 Jun, 2023 - Comments: 0

An explosion of data in automotive, cloud, and AI are altering the fundamentals of memory design. One size no longer fits all, as memory is used for a broader set of applications, from automotive and cloud to consumer devices. Anand Theruvengadam, director of product management at Synopsys, talks about the impact of big data applications on density, memory stacking, and growing concerns about r... » read more

IEDM: Backside Power Delivery
By Paul McLellan - 09 Mar, 2023 - Comments: 0

One part of the short course that I attended at IEDM in December was about backside power delivery networks. It was presented by Gaspard Hiblot of imec and titled "Process Architectures Changes to Improve Power Delivery." The presentation is co-credited with Geert Hellings and Julien Ryckaert. I should preface this post with the fact that this presentation was 80 slides long and so I will only... » read more

Challenges In Backside Power Delivery
By Laura Peters - 17 Nov, 2022 - Comments: 0

One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions. Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on t... » read more

Beyond 5nm: Review of Buried Power Rails & Back-Side Power
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

A new technical paper titled "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes" is presented by researchers at UT Austin, Arm Research, and imec. Find the technical paper here. Published July 2022. S. S. T. Nibhanupudi et al., "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes," in IEEE Transactions... » read more

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