# Stitching Together A Multi-Layer PCB PDN

Understanding current distribution is essential to minimize waste and avoid overdesigned via arrays.

A printed circuit board (PCB) is much like a complicated city, with a myriad of intertwined pathways for data signals and power. To meet the electric current needs of modern, high-powered integrated circuits (ICs), the power distribution network (PDN) usually consists of wide power planes on multiple layers to provide a low-resistance path for power delivery. These planes are stitched together with arrays of vias. Understanding how the current is divided in such arrays is essential to minimizing waste and needlessly overdesigning the array, and simulation of such arrays can provide valuable insight into optimizing them.

Some simple resistance calculations will facilitate a basic understanding of PDN current distribution. Resistance is equal to resistivity divided by area multiplied by length. R = rho*L/A. For copper, resistivity (rho) is 1.724×10^-8 ohm-m, or 6.787×10^-4 ohm-mil. For a cross-section of copper trace or plane, the area (A) = width * height, where height is determined by the copper weight (1/2-oz., 1-oz, etc.). If we set the width equal to length, which makes the piece of copper a square, they will cancel out of the resistance formula. Thus, we can determine the resistance for a “square” of copper based on the copper weight. For example, assuming a 1-oz. copper plane is 1.35 mils thick, that means a “square” of that plane has a resistance of 0.503 mΩ. A via, on the other hand, has a ring-shaped cross-section, with a resistance that would be: rho * length / [pi*(drill size / 2)^2 – pi*((drill size – (plating thickness*2))/2)^2]. So for a via with an 8-mil drill via with 1/2-oz (0.7-mil) plating that goes all the way through an 82-mil board, the resistance of that via would be 3.47 mΩ end to end. That is close to moving through seven “squares” of a 1-oz. plane, which would be 3.52 mΩ.

Fig. 1: Using squares of plane to determine resistance through plane shapes.

In most board designs, the resistance of a via tends to be much lower than moving through a square of plane. Because of that, the position of a via matters more than anything else in determining how much current will pass through it.

In the example shown in figure 2, there are two main “legs” of a power distribution network (PDN) connected by a 5×5 array of stitching vias. Current flows from the left of the top leg to the bottom of the right leg. The plane shapes are on layers VCC1 and GND1 in the stackup, separated by only 3 mils, so each via presents only 8.8 µΩ or 0.0088 mΩ of resistance. That means there is over 50 times as much resistance (503 µΩ) going through a square of plane than there is going through a via. This means that the position of the via will be the most important factor in determining the current through it, meaning there is a high likelihood of having very different currents in different vias in the array.

Fig. 2: PDN with layers connected by short, fat vias.

This hypothesis is confirmed by looking at the results of the simulation shown in figure 3. The current-density plot shows the bulk of the current being concentrated on the inside corner of the bend. Because the via resistance is so much less than the plane resistance, the current would rather turn the corner tightly than spread out to the other vias, as that provides the minimum path of resistance. The via-current plot shows how the via current within the array varies from 9.7 A down to 0.003 A.

Fig. 3: Results of analysis on PDN with layers connected by short, fat vias.

In a contrasting example, the connected plane layers are on the top and bottom layers, separated by most of the thickness of the board (92.1 mils). The stitching vias, still in a 5×5 array, are grouped in a much denser pattern and each have 3.737 mΩs of resistance. That means there is less than 1/7th as much resistance (0.503 mΩ) going through a square of plane than there is going through a via. Since a via is more resistive than going through the copper plane, current will spread more evenly amongst the vias to minimize the total resistance. In other words, the path of least resistance will be through many vias in parallel.

This hypothesis is confirmed by looking at the results of the simulation in figure 4. The current-density plot shows the concentration of current over the entire via array at the center of the junction of the two legs. Because the via resistance is high and the vias are more densely packed, current will spread more evenly amongst the vias. The via-current plot shows how the via current does not vary much within the array — it goes from a maximum of 2.691 A to a minimum of 1.611 A.

Fig. 4: Results of analysis on PDN with layers connected by long, skinny vias.

A comparison of these two examples reveals two different extremes of how currents can be distributed in via arrays. In the extreme case of the long, skinny vias that are densely packed, currents are much more equally balanced. There is a difference of only about 1 A across the via array. However, this is rarely the case in a real board design, so a much more uneven distribution is to be expected, as in the other case where there is a difference of almost 10 A.

For more details, you can download the full paper Distribution of Currents in Via Arrays from Siemens.