tag: vias

Breaking The Copper Bottleneck With Molybdenum Hybrid Metallization
By Taeyeon Oh - 18 Sep, 2025 - Comments: 0

Scaling the back end of line (BEOL) in advanced semiconductor logic devices is a major challenge. Metal lines and via filling in BEOL have historically used copper (Cu) as the electrical conductor. But as device dimensions shrink, Cu use has become problematic. The small critical dimensions (CD) of the Cu metal lines and vias in the latest BEOL structures have created an increase in resistance,... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

Maximizing Signal Integrity: Fine-Tuning Via Impedance In HDFO Architectures
By Tsung Ting Lee - 22 May, 2025 - Comments: 0

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most of the electrical properties cannot be measured by instruments. Therefore, this study uses the indirect method to determine the impedance information of the via and match the impedance. Since the v... » read more

Research Bits: Dec. 16
By Jesse Allen - 16 Dec, 2024 - Comments: 0

Soft liquid metal vias Researchers from Virginia Tech and University of Pennsylvania found a way to create soft, flexible electric connections through circuit layers. The method could be used for soft robotics and wearable devices. The technique uses liquid metal microdroplets to create a stair-like structure that forms soft vias and planar interconnects through and across circuit layers wi... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance
By Jimmy Tien - 10 Aug, 2023 - Comments: 0

As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

Stitching Together A Multi-Layer PCB PDN
By Patrick Carrier - 25 May, 2023 - Comments: 0

A printed circuit board (PCB) is much like a complicated city, with a myriad of intertwined pathways for data signals and power. To meet the electric current needs of modern, high-powered integrated circuits (ICs), the power distribution network (PDN) usually consists of wide power planes on multiple layers to provide a low-resistance path for power delivery. These planes are stitched together ... » read more

The Path To Known Good Interconnects
By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Characterization Of HEMT Vias
By KLA - 08 Nov, 2022 - Comments: 0

The Zeta-Series optical profilers provide accurate measurement and automated analysis of high aspect ratio structures such as HEMT vias using non-destructive and high throughput metrology techniques.  Introduction Wide bandgap semiconductor materials are extremely attractive for use in power electronics, due to their performance capability at high temperature, power and frequency. Among wide... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach
By Brewer Science - 19 Aug, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonst... » read more

Lower Resistance Protects Against Failure In IC Design
By Fady Fouad - 28 May, 2020 - Comments: 0

By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

← Older posts

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy