Lower Resistance Protects Against Failure In IC Design

By Fady Fouad, Esraa Swillam, and Jeff Wilson

When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number and impact. Because this increased resistance has a direct impact on both reliability and yield, designers must find ways to keep it in check to reduce the risk of IC failures.

With the power grid width being pre-determined, the most effective means of lowering resistance is to add vias. Traditionally, adding vias to a layout is accomplished using custom scripts. However, at advanced nodes, the increasing complexity of via rules required to control different stacks, complex spacing rules, different enclosures, and via count per width make the use of custom scripts too complex and time-consuming for most companies.

Electronic design automation (EDA) companies continuously evaluate IC design process flows to identify opportunities for improvement and automation. By adding the PowerVia utility to its Calibre YieldEnhancer design for manufacturing (DFM) toolset, Mentor, a Siemens business, replaced those custom via scripts with a “push-button” via set-up and insertion process. This automated flow inserts additional correct-by-construction vias as needed to reduce IR drop and EM issues, and improve design performance and reliability. To evaluate the effectiveness of the new approach, Mentor collaborated with integrated circuit (IC) design companies to implement and evaluate the use of the PowerVia solution in production designs.

Push-button via insertion

The PowerVia utility incorporates foundry manufacturing requirements to determine correct-by-construction constraints for via insertion. This reliance on foundry specifications means the PowerVia utility can work with any foundry, for any process, while ensuring that the inserted vias are design rule checking (DRC) and layout vs. schematic (LVS) compliant. The PowerVia utility also supports Calibre multi-threading and hyperscaling, enabling it to work efficiently on designs of any size and complexity.

Process flow

At invocation, the design team supplies the targeted net names and metal stack. The basic PowerVia flow then performs the following steps:

1. Scans the design using the supplied net name(s).
2. Locates candidate locations for via insertion by identifying layer intersections of the same net.
3. Using the foundry requirements, inserts as many DRC/LVS-clean vias as possible at these locations (Figure 1).

Figure 1: Automated via insertion using the PowerVia utility.

Via type selection

The additional vias are selected by the PowerVia utility based on the type of layers intersection. For example, as shown in Figure 2, via Vx is added at the Mx, MX+1 intersection.

Figure 2: The type of via inserted is determined by the intersection layers type.

Designers can also designate the insertion of specific via types (large/bar/square) for a given via layer, either individually or in combination. For example, if designers select a combination of bar/square vias for via layer 1, a bar via is inserted at all v1 intersections where possible; otherwise, a square via is inserted. For via layer 2, if they only specify a bar via, all v2 intersections get a bar via.

Customization

Multiple custom options can be selected by the design team as needed, such as

• Skip insertions on selected requirements (e.g., block insertion)
• Enable analog-specific features, such as controlled edits on metals
• Use a custom flow to link to circuit description language (CDL) netlist

Output

Each PowerVia run generates a debugging database, enabling the design team to understand the generated results relative to the design under test:

• PWR/GND/Other (user-defined) nets extracted
• Other signal lines
• Existing vias
• Potential fill areas for each via layer
• PowerVia added vias

Figure 3 illustrates the complete PowerVia flow. While the goal in this collaboration was to evaluate the addition of DRC/LVS-clean vias to power and ground nets, the PowerVia utility can also be used to add vias to clocks and wide bus nets.

Figure 3: PowerVia utility automated via insertion flow can increase design reliability and reduce IR drop.

Results

The PowerVia utility was used by IC design companies on a variety of production designs. In a typical advanced node design, the PowerVia utility was implemented for multiple blocks. Design teams first used manual techniques to add as many vias as possible before applying the PowerVia utility. Table 1 shows the number of vias added solely as a result of the PowerVia utility (i.e., beyond the manual via insertions). The results show significant via addition, even at the final stage.

Table 1. PowerVia automated via insertion

Using the PowerVia utility in this design resulted in a ~5-10% improvement in both EM and IR drop results. In additional experiments, Mentor found that adding vias to power nets using the PowerVia utility returned up to a 68% reduction in current density violations. In the design shown in Figure 4, the M12-M13 vias inserted by the PowerVia utility on differential power nets provided a significant improvement in IR results in that region. These vias were not present in the initial design.

Figure 4: PowerVia automated via insertion on differential power nets.

Conclusion

At advanced nodes, increasing resistance means IR drop and EM issues have become significant performance and reliability detractors. Adding vias to the layout is the most effective means of reducing the impact of these effects, but traditional custom scripts are difficult and time-consuming to create and manage, without the guarantee of correct by construction vias.

Mentor introduced the Calibre YieldEnhancer PowerVia utility, an automated solution that provides DRC/LVS-clean via insertion with push-button invocation. The PowerVia utility uses manufacturing requirements provided by the foundry to maximize the insertion of correct-by-construction vias.

Results showed significant improvements in EM/IR drop results, including substantial reductions in current density violations, while ensuring that the additional vias were correct by construction. Minimizing the growth of resistance in advanced nodes designs by incorporating tools like the PowerVia utility into their process flow enables design companies to substantially improve design performance and reliability with minimal impact to workloads and design schedules. In this instance, less is definitely more!

Esraa Swillam is a senior product engineer in the Design to Silicon division of Mentor, a Siemens business, supporting Calibre DFM products. She works closely with software engineering, product marketing, field engineering, and customers to define and characterize new tools and capabilities that improve and augment design verification and optimization flows. Swillam received her B.Sc. in Electrical Engineering from Ain Shams University, and an M.Sc. in Electronics Engineering from the American University in Cairo.

Jeff Wilson is a product management director for DFM applications in the Calibre organization at Mentor, a Siemens business. He is responsible for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Wilson previously worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.