The Implementation Of Embedded In-Chip Sensing Fabrics In Today’s Cutting-Edge Technologies


This whitepaper takes a comprehensive look at the implementation of Embedded Sensing Fabrics in today’s cutting-edge technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of... » read more

Lower Resistance Protects Against Failure In IC Design


By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

Reducing IR And EM Issues With Automated Via Insertion


IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Power Challenges In ML Processors


The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

Interdependencies Complicate IC Power Grid Design


Creating the right power grid is a growing problem in leading-edge chips. IP and SoC providers are spending a considerable amount of time defining the architecture of logic libraries in order to enable different power grids to satisfy the needs of different market segments. The end of Dennard scaling is one of the reasons for the increased focus. With the move to smaller nodes, the amount of... » read more

Monitoring Heat On AI Chips


Stephen Crosher, CEO of Moortec, talks about monitoring temperature differences on-chip in AI chips and how to make the most of the power that can be delivered to a device and why accuracy is so critical. » read more

Backside Power Delivery as a Scaling Knob for Future Systems


Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO explorat... » read more

Optimizing Power For Learning At The Edge


Learning on the edge is seen as one of the Holy Grails of machine learning, but today even the cloud is struggling to get computation done using reasonable amounts of power. Power is the great enabler—or limiter—of the technology, and the industry is beginning to respond. "Power is like an inverse pyramid problem," says Johannes Stahl, senior director of product marketing at Synopsys. "T... » read more

Why Chips Are Getting Noisier


In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Timing Is Of The Essence


Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

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