Balancing IR Drop Unpredictability With Post-Silicon Flexibility

Increased wire resistance and voltage-sensitive paths call for a new approach to mitigating voltage droop.


The concept of IR drop in silicon chips has always been a crucial aspect of chip design. However, recent technological trends and the emergence of new challenges, such as voltage-sensitive paths, have introduced a degree of uncertainty in predicting and effectively managing IR drop. These uncertainties are driving the need for a more flexible approach in mitigating on-die voltage droop.

Increasing unpredictability in resistance and capacitance

The new landscape of IR drop in silicon chips is largely attributed to the increase in resistance within the semiconductor interconnect as technology nodes scale down from 28nm to 3nm. This resistance increment is primarily due to the reduction in cross-sectional area of the metal lines, constraining the current flow and leading to a significant increase in voltage (V = IR, Ohm’s Law) drop across the interconnect. Moreover, as we transition to advanced nodes, wire resistance becomes exponentially more prominent, as figure 1 shows. With an increase in wire resistance, and assuming a constant current, the corresponding IR drop will also proportionally increase, thereby becoming a more significant consideration in the overall design.

Fig. 1: Exponential wire resistance vs process node[1].

As transistors shrink, critical paths become more sensitive towards wire resistivity. Between 10nm and 7nm, delay sensitivity (change in gate/wire delay vs change in wire resistance) almost triples[2], as figure 2 shows. This increased sensitivity trend is expected to grow exponentially, leading to expanded uncertainty in pre-silicon simulation. Even the most minute process variation can have drastic gate delay effects that may not be captured in pre-silicon modeling.

Fig. 2: Delay sensitivity to wire resistance and capacitance in 10nm and 7nm[2].

In addition to the increased resistance, another element of the evolving landscape is operating voltage, which continues to decrease with every technology node. As the operating voltage decreases, the noise margin also shrinks, making the circuit more susceptible to voltage fluctuations. This heightened sensitivity of advanced node libraries to supply voltage fluctuations compounds the uncertainty surrounding IR drop management.

Voltage-sensitive paths: Another piece of the puzzle

Voltage-sensitive paths are adding another layer of complexity to the IR drop puzzle in modern silicon chip design. These paths are created due to a combination of standard cells, slews, and loadings, which are highly sensitive to variations in voltage. The more these paths are prone to voltage fluctuation, the higher the probability of timing failures. In 7nm, designers are seeing up to a 25% variation in high-VT cell delay for a 10mV IR drop at 0.5V[3]. Interestingly, voltage-sensitive paths are not always the most critical paths. For instance, a non-critical path that has historically been overlooked might suddenly become a point of timing failure when subjected to voltage fluctuations[4].

This unpredictability posed by voltage-sensitive paths is a stark reminder of the challenges faced by conventional signoff methods. Traditional methodologies rely heavily on identifying and optimizing critical paths, which might not always be the most voltage-sensitive. Therefore, even if a chip passes the conventional signoff process, it may still have “soft” failures due to unexpected timing glitches[5]. A soft failure usually causes the chip to run at a slower frequency or use more power than expected. To solve this problem, the industry needs to rethink its approach to evaluating timing and power, ensuring that voltage-sensitive paths are given due attention in the design process. This would require a more detailed understanding of the nuances of chip design, pushing the boundaries of existing design rules.

Pin the tail

Silicon design teams are facing an increasingly complex and uncertain landscape when it comes to managing IR drop. The advent of advanced technology nodes has heightened the unpredictability of resistance, capacitance, and the emergence of voltage-sensitive paths. These uncertainties can reduce the accuracy of hotspot correlation between pre-silicon simulations and actual silicon.

How do you combat uncertainty? With flexibility. Design teams can use programmable droop response systems to effectively serve IR drop hotspots by scattering dozens of droop detectors across a chip to improve the efficacy of their droop response system (this requires area-effective solutions that scale with process technology). Post-silicon programmability allows design teams to vary droop response sequence, length, and behavior to uniquely mitigate each droop profile.

As we navigate the era of advanced technology nodes, embracing a more dynamic and comprehensive approach to IR drop management is no longer a luxury, but a necessity. With tools like the Aeonic Integrated Droop Response System, we’re making strides towards a future where we can more effectively mitigate voltage fluctuations, improving the reliability and performance of next-generation silicon chips.


[1] K. Moraes, “Classic Moore’s law scaling challenges demand new ways to wire and integrate chips,” Applied Materials, (accessed Aug. 12, 2023).

[2] Z. Tokei, “End of cu roadmap and beyond cu,” 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2016. doi:10.1109/iitc-amc.2016.7507738

[3] M. Swinnen, “Designers face growing problems with on-chip power distribution,” Semiconductor Engineering, (accessed Aug. 12, 2023).

[4] S. Pant and D. Blaauw, “Static timing analysis considering power supply variations,” ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. doi:10.1109/iccad.2005.1560095

[5] K. Heyman, “EDA’s role grows for preventing and identifying failures,” Semiconductor Engineering, (accessed Aug. 14, 2023).

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