tag: voltage droop

Remote Droop Detection And Response Use Case
By Movellus - 28 Feb, 2024 - Comments: 0

While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialized and varied workloads. However, this asymmetry, combined with rapid provisioning changes, can lead to global voltage droops on the SoC resulting in potenti... » read more

Which Data Works Best For Voltage Droop Simulation
By Ann Mutschler - 15 Jan, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

Analog Design Complicates Voltage Droop
By Ann Mutschler - 27 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

Managing P/P Tradeoffs With Voltage Droop Gets Trickier
By Ann Mutschler - 14 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop/IR drop with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight Technologies; Venkatesh Santhanagopalan, product manager at Movellus; Joe Davis, senior director for Calibre interfaces and mPower EM/IR... » read more

Balancing IR Drop Unpredictability With Post-Silicon Flexibility
By Aakash Jani - 24 Aug, 2023 - Comments: 0

The concept of IR drop in silicon chips has always been a crucial aspect of chip design. However, recent technological trends and the emergence of new challenges, such as voltage-sensitive paths, have introduced a degree of uncertainty in predicting and effectively managing IR drop. These uncertainties are driving the need for a more flexible approach in mitigating on-die voltage droop. Increa... » read more

Mitigating Voltage Droop
By Aakash Jani - 13 Jun, 2023 - Comments: 0

Voltage droop, also known as IR drop, is a phenomenon that occurs when the current in the power delivery network abruptly changes due to workload fluctuations. This can lead to supply voltage drops across system-on-chips (SoCs) which can cause severe performance degradation, limit their energy efficiency, and in extreme cases can cause catastrophic timing failures. To avoid these issues, conven... » read more

Waking And Sleeping Create Current Transients
By Bryon Moyer - 10 Dec, 2020 - Comments: 0

Silicon power-saving techniques are helping to reduce the power required by data centers and other high-intensity computing environments, but they’ve also added a significant challenge for design teams. As islands on high-powered chips go to sleep and wake up, the current requirements change quickly. This happens in a few microseconds, at most. The rapid change of loading creates a challen... » read more

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