System architects can mitigate droops with integrated droop response systems, which adapt dynamically to voltage droops (IR drops).
While sea of processor architectures feature a stamp and repeat design, per-core workloads aren’t always symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialized and varied workloads. However, this asymmetry, combined with rapid provisioning changes, can lead to global voltage droops on the SoC resulting in potential logic glitches across the die.
A global voltage droop occurs when there is a sudden rush of switching activity driven by fluctuating workloads, which creates a drop in the supply VDD and might raise the ground voltage level (also known as a ground bounce). A localized voltage droop might result in a global voltage droop and cause setup and hold time violations causing transient glitches and potentially catastrophic mission-mode failures.
System architects can now mitigate droops with integrated droop response systems, which adapt dynamically to voltage droops (IR drops). The technique requires a programmable clock and tightly coupled droop detectors to create a fully self-contained droop response system.
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