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Architectural Power Issues

Power reduction at the architectural level


When power targets are aggressive, it is important to design for low-power intent from inception. The earlier that power is considered in the design, the larger the savings can be. The majority of power is determined by decisions made at or before synthesis. Exploring various micro-architectures and their associated power architectures is possible only early in the design flow; it is too costly and time-consuming during implementation.

A key decision in creating a low-power design is choosing the most appropriate micro-architecture, the state and processing elements, and how data flows. Especially at smaller geometries, the tradeoffs among power, performance, and silicon area are not always intuitive.

For example, the IEEE 802.11a standard for wireless communications transmitters includes functional blocks such as the controller, scrambler, convolutional encoder, interleaver, and IFFT. The IFFT performs a 64-point Inverse Fast Fourier Transform (IFFT) on the complex frequencies.

Alternative micro-architecture implementations include a purely combinational version, a synchronous pipelined version, and five super-folded pipelined versions with 16, 8, 4, 2, and 1 bfy4 nodes, respectively.

The amount of energy required to process one OFDM symbol, with performance held constant, ranged from 4mW to over 34mW. Surprisingly, the 802.11 transmitter block design using the purely combinational IFFT consumed the least power, while the super-folded pipelined version using only a single bfy4 node consumed 8.5X more power (Holly Stump and George Harper. ESL Synthesis + Power Analysis = Optimal Micro-Architecture, Chip Design Magazine, Jan. 2007). During and after selecting the best micro-architecture, designers must trade off power, performance, and area (price of the silicon) with different power-saving techniques. But these techniques are only as effective as the micro-architecture allows.

Page contents originally provided by Cadence Design Systems