Utilizing Clock-Gating Efficiency To Reduce Power In RTL Designs

A better approach than optimizing multiple design iterations.


With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are gated.

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