Author's Latest Posts


Solving the E/E Dilemma of Electric And Autonomous Vehicles


As automotive manufacturers and suppliers develop advanced technologies to realize the trends of autonomy, connectivity, electrification, and shared mobility, they are encountering a number of dilemmas as each trend drives different aspects of vehicle development. This paper will focus on the E/E design challenges created by electric and autonomous vehicles, and describe a multi-domain architec... » read more

Reducing IR And EM Issues With Automated Via Insertion


IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Machine Learning At The Edge


Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

AI Chip DFT Techniques For Aggressive Time-To-Market


AI chips have aggressive time-to-market goals. Designers can shave significant time off of DFT and silicon bring up using the techniques described in this paper. Leading AI semiconductor companies have already had success with Tessent DFT tools. To read more, click here. » read more

The Criticality Of The E/E Architecture


Modern vehicles are highly sophisticated systems incorporating electrical, electronic, software and mechanical components. Mechanical systems are giving way to advanced software and electronic devices, driving automakers to innovate and differentiate their vehicles via the electric and electronic (E/E) architecture. Future architectures need to be scalable across vehicle platforms, flexible to ... » read more

Parasitic Extraction of MIM/MOM Capacitors In Analog/RF Designs


The extensive use of MIM/MOM capacitors in analog/RF designs presents designers with extraction challenges that typically require multiple extraction techniques. The Calibre xACT platform offers analog/RF designers the fast performance of a rule-based extraction engine, and the capacity and performance of a field solver, to efficiently extract all parasitic components in a timely manner, with t... » read more

Interconnect Inductance Extraction For Analog And RF IC Designs


Increasing operating frequencies for analog/RF designs mean interconnect inductance parasitic extraction is now required to ensure accurate circuit performance and high reliability. Automated field solver-based inductance extraction of both self and mutual parasitics enables IC companies to deliver analog/RF chips that provide the intended level of performance and reliability. To read more, ... » read more

Optimal End-to-End DFT Automation With Tessent Connect


With the growth in design size and complexity, DFT engineers began adopting new methods to reduce DFT implementation time, reduce test costs, and reduce risks to design schedules by removing DFT from the critical path to tapeout. The primary method to accomplish large improvements to DFT efficiency is through a divide-and-conquer approach supported by Tessent’s RTL-based, hierarchical DFT ins... » read more

Push-Button FMEDAs for Automotive Safety


Automotive designs require functional safety analysis, typically accomplished using Failure Modes, Effects and Diagnostic Analysis (FMEDA), used to determine each safety goal’s diagnostic coverage. Writing an FMEDA is a highly tedious task, so we share a push-button solution for creating and automating the FMEDA process, giving engineers more time to focus on exploring design safety readiness... » read more

Renesas Solves High-Level Verification Challenges Using Formal Equivalence Checking


A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the form... » read more

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