Author's Latest Posts


Formally Ensuring Equivalence Between C++ And RTL Designs


Moving untimed C++ design descriptions through a High-Level Synthesis (HLS) flow, designers wonder if the generated, timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that these changes no longer meet their original specifications. They could create testbenches and run verification at ... » read more

Unveil The Mystery Of Code Coverage In Low-Power Designs: Achieving Power Aware Verification


This paper discusses challenges in code coverage of low-power designs and approaches to overcome those challenges. Also explained is how total coverage results can be visualized in order to achieve verification closure in significantly less time. To read more, click here. » read more

Tessent Hierarchical ATPG Reference Flow for Arm Cortex-A75


Arm and Mentor have jointly developed a reference flow for a hierarchical DFT and ATPG implementation with Tessent for any Arm subsystem based on Cortex A-series IP. The reference flow, described in this paper, provides documentation, seamless interfaces, and scripts that accelerate the implementation of a hierarchical test solution. Arm and Mentor are dedicated to enabling customer success, re... » read more

Toshiba Verifies Thermal Contribution In Motor Control Driver ICs


High output current ICs usually generate a lot of heat from the driver transistor, which affects the surrounding circuits. Therefore, it is important to take into account the transient heat based on the output current level when designing applications such as engine throttles or on/off switches for engine bulbs. In this whitepaper, the Toshiba team discusses how they used the Eldo circuit simul... » read more

AI Accelerator Ecosystem: An Overview


Companies worldwide trust the Catapult HLS Platform for designing and verifying machine learning accelerators and connecting them to systems. But, Mentor has taken a big step farther and offers an AI accelerator ecosystem that provides AI designers with an environment to jumpstart their projects. Based on years of working with designers, this ecosystem provides resources from IP libraries to fu... » read more

Selecting A Portable Stimulus Application Focal Point


The "axes of reuse" are a powerful way to identify a focal point for your application of Portable Stimulus. Picking a focal point helps to identify needed resources and identify the gap between what is needed and what already exists in your organization. Picking an initial focal point for applying Portable Stimulus doesn’t preclude expanding the application of Portable Stimulus in the future.... » read more

Meeting ISO 26262 Requirements Using Tessent IC Test Solutions


As the industry moves towards greater automation in vehicles, suppliers of the ICs used to drive the automotive electronic systems are rapidly adopting solutions to meet ISO 26262 requirements. The Tessent family of IC test products offers the highest defect coverage, in-system non-destructive memory test, hybrid ATPG/Logic BIST, and analog test coverage measurement. These technologies add up t... » read more

Addressing IC Reliability Issues Using Eldo


Advanced, short-geometry CMOS processes are subject to aging that causes major reliability issues that degrade the performance of integrated circuits (ICs) over time. Degradation effects causing aging are hot carrier injection (HCI) and negative bias temperature instability (NBTI), in addition to positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). Below ... » read more

IC Design: Preparing For The Next Node


The challenges of preparing for the next process node require constant preparation by the foundries, the EDA industry, and the design companies. Learn how Mentor works to prepare the Calibre nmPlatform for each “next node,” and ensure that its customers have the tools and performance they need to succeed. To read more, click here. » read more

Finding Code Problems Before High-Level Synthesis


In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology. But, it is extremely important that the high-level C++ model is correct. In addition, the C++ language has ambiguities that can be tough to catch during simulation. Even if correctly written, the high-level model could be cod... » read more

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