Author's Latest Posts


Achieving Functional Safety For Autonomous Vehicle SoC Designs


Autonomous vehicle systems will be expected to meet rigorous safety standards regarding many aspects of system design and performance. One set of these standards, known as functional safety, focuses on the safety and reliability of the electrical and electronic systems within the vehicle, and the system-on-chip (SoC) devices in particular. As the complexity of these devices grows, autonomous ve... » read more

Enhancing IO Ring Checks For Consistent, Customizable Verification


The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

Addressing The Challenges Of Reset Verification In SoC Designs


This paper presents commonly occurring challenges involved in reset tree verification and their solutions. We lay out a three part approach to build a complete solution that combines static analysis of the design structure, RTL simulation with X-propagation, and formal verification. The paper includes results from testing this solution on a customer design. To read more, click here. » read more

Simplifying Silicon Bring-Up And Debug On ATE equipment With ATE-Connect


The silicon bring-up process is ripe for improvement. Tessent SiliconInsight with ATE-Connect technology eliminates communication barriers between proprietary tester-specific software and DFT platforms, which accelerates debug of IJTAG devices, speeds product ramps, and reduces time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence. Read mo... » read more

Emulation Fills The Pre-Silicon Verification Gap For Autonomous Vehicles


Veloce emulators provide the scale and performance to ensure that automotive applications run smoothly, safely, and securely. This paper describes how emulation is used to run realistic driver scenarios, investigate vehicle dynamics, and analyze power and communications metrics — all in a platform that virtualizes the design and allows both hardware and software to be tested together or separ... » read more

5G Verification Is Impossible Without Emulation


Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced with and having the tight performance characteristics needed for successful integration into a 5G sy... » read more

Embedded Multicore: Enablement Of Heterogeneous OSes And Mixed Criticality Systems


The implementation of multicore embedded systems is becoming increasingly common. The decision to realize a design using multiple processors may be influenced by a number of factors; broadly these are technical goals to attain, a time to market to achieve, and target design and production costs. Using multicore in a design requires a number of key decisions, which, as with most embedded systems... » read more

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs


Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an RTL-based hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent products. The focus is on the techniques and automation of... » read more

Implementing A Multi-Domain System


IoT systems are multi-domain designs that often require AMS, Digital, RF, photonics and MEMS elements within the system. Tanner EDA provides an integrated, top-down design flow for IoT design that supports all these design domains. Learn more about key solutions that the Tanner design flow offers for successful IoT system design and verification. To read more, click here. » read more

A Specification-Driven Methodology For The Design And Verification Of Reset Domain Crossing Logic


Reset architectures have increased in complexity along with SoC designs. Sadly, traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a three-step specification-driven methodology that provides a requirements-based approach for reset domain crossing design and verification. To ... » read more

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