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Random Directed Low Power Coverage Methodology


This paper proposes a low-power coverage methodology based on the recently introduced UPF 3.0 low-power information model HDL package. Verification engineers can use this approach to achieve low-power coverage closure earlier. We share relevant case studies and examples using the methodology to solve low-power verification problems. It also discusses the benefits of this approach and its advant... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology


This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

Using Hypervisor For IVI And AUTOSAR Consolidation On An ECU


Current approaches used to tackle the complexities described earlier in this paper (cockpit domain units) are both cost-prohibitive and lacking in performance. Utilizing virtualization in automotive software architecture provides a better approach when taking on these complexities. This can be achieved by encapsulating different heterogeneous automotive platforms inside virtual machines running... » read more

Configurable, Easy-To-Use, Packaged Reliability Checks


Using a packaged checks flow lets designers quickly select, configure and run custom reliability checks and check combinations to help design companies achieve today’s demanding time-to-market schedules while ensuring product reliability. To read more, click here. » read more

Machine Learning At The Edge


Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

Improving Test Pattern Compression With Tessent VersaPoint Test Point Technology


Mission-critical applications within markets such as transportation and medical devices require higher overall manufacturing test quality, but that often means more test patterns, data volume, and longer test times. Embedded test compression helps, but using VersaPoint test point technology results in 46X compression ration over what is possible with Tessent TestKompress alone. To read more,... » read more

Achieving Functional Safety For Autonomous Vehicle SoC Designs


Autonomous vehicle systems will be expected to meet rigorous safety standards regarding many aspects of system design and performance. One set of these standards, known as functional safety, focuses on the safety and reliability of the electrical and electronic systems within the vehicle, and the system-on-chip (SoC) devices in particular. As the complexity of these devices grows, autonomous ve... » read more

Enhancing IO Ring Checks For Consistent, Customizable Verification


The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

Addressing The Challenges Of Reset Verification In SoC Designs


This paper presents commonly occurring challenges involved in reset tree verification and their solutions. We lay out a three part approach to build a complete solution that combines static analysis of the design structure, RTL simulation with X-propagation, and formal verification. The paper includes results from testing this solution on a customer design. To read more, click here. » read more

Simplifying Silicon Bring-Up And Debug On ATE equipment With ATE-Connect


The silicon bring-up process is ripe for improvement. Tessent SiliconInsight with ATE-Connect technology eliminates communication barriers between proprietary tester-specific software and DFT platforms, which accelerates debug of IJTAG devices, speeds product ramps, and reduces time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence. Read mo... » read more

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