Author's Latest Posts


Low Power Coverage


Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug


Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

Autonomy, Electrification And The Rise Of Model-Based EE Design


Powerful software that automatically transforms input models into deterministic outputs is transforming automotive electrical and electronics (EE) design. Martin O'Brien and Dan Scott set the stage for Mentor's advanced generative engineering approach. To read more, click here. » read more

Comprehensive CDC Verification Using Advanced Hierarchical Data Models


In this paper, we describe the hierarchical data model (HDM), which is a performance efficient alternative to the traditional flat CDC verification flow. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly re-used across releases and across designs wherever the IP i... » read more

The Veloce Strato Platform: Unique Core Components Create High-Value Advantages


The Veloce Strato Emulation platform has sufficient execution speed, full visibility capabilities and ease-of-use in model creation and model updates to span the entire range of needs throughout the life of the design development process. To read more, click here. » read more

Putting “Design” Back Into Design For Test In PCB Products


Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-relat... » read more

18th Century Technology For Modern Medical IoT


Back in 1790, Luigi Galvani was dissecting a frog and noticed that he could cause its leg to move when touching a nerve with two probes. He called this phenomenon “animal electricity.” This concept was soon refined over time to become the voltaic cell, the foundation concept of the potato clock, fondly known by all engineers. Who knew that this cell would be leveraged to create an ingestibl... » read more

Choosing A Format For The Portable Stimulus Specification


The Accellera Systems Initiative is currently defining a Portable Stimulus Specification (PSS) standard for verification models that can be used to generate appropriate tests for all levels and platforms automatically. The current draft of the standard includes two alternative input formats for these models. This paper examines the merits and challenges of both formats. To read more, click h... » read more

Alchip Minimizes Dynamic Power For High-Performance Computing ASICs


Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design... » read more

Package Designers Need Assembly-Level LVS For HDAP Verification


While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced LVS-like verification techniques that can move across the entire package to ensure proper connectivity and perfo... » read more

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