Author's Latest Posts


SystemVerilog Constraints


This paper looks at two of the most common issues when constraint solver results do not match your intent: Not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra and not understanding the affect probability has on choosing solution values. Coding recommendations for improving your code to get better results are provided. To read more, click here. » read more

The Advantages Of MBSE-Driven E/E Architecture


Vehicles in all sectors are growing in complexity as OEMs develop sophisticated platforms with growing levels of automation and connectivity. To cope with this growing complexity, automotive, aerospace and commercial vehicle OEMs must evolve their architectural design processes to leverage MBSE and the digital thread. Today’s E/E system engineering solutions help companies implement MBSE by p... » read more

Increase LVS Verification Productivity In Early Design Cycles


With the innovative Calibre nmLVS-Recon early verification tool, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging. To read more, click here. » read more

Efficient Sensitivity-Aware Assessment Of High-Speed Links Using PCE And Implications For COM


This technical white paper, originally presented at DesignCon, investigates the challenges of increased data rates and reduced margins in high-speed link design. Section 1: Introduction Section 2: State of the Art Link Evaluation and Assessment of Parameter Variability Section 3: Proposed Modeling Framework Section 4: Sensitivity Analysis of a High-Speed Interconnect Section 5: Conclusio... » read more

Critical Area-Based Test Pattern Optimization For High-Quality Test


Among the challenges for DFT engineers is how to set a target metric for ATPG and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected doesn’t consider the likelihood of one fault occurring compared to another. Tessent developed total critical area ATPG technology that enables the sorting and ordering of patterns based on their likelihood... » read more

Accelerate Time To Market With Calibre nmLVS-Recon Technology


One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS-Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market. To rea... » read more

PCIe Simulation Speed-Up Using Mentor QVIP With PLDA PCIe Controller For DMA Applications


In this case study, PLDA explains how verification engineers can use Mentor’s Questa Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines. The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe interfaces with multiple A... » read more

Re-Imagining Electrical System Design


Electrical system complexity is reaching a tipping point across industries, from modern passenger vehicles to sophisticated industrial machines that can now contain nearly 5,000 wiring harnesses. The electrical systems of these machines contain multiple networks, thousands of sensors and actuators, miles of wiring and tens of thousands of discrete components. Designing these complex systems is ... » read more

Multi-Mode Clock Domain Crossing Verification Enables Analysis Efficiency And Accuracy


This paper shows how automated modal CDC analysis is used to exhaustively verify CDC issues in all test and operational modes of an SoC with multiple IPs. This new approach automatically consolidates all results from each mode, making issues very easy to interpret and debug. What took days and weeks with the prior manual approach now takes only a few hours. To read more, click here. » read more

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC


To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

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