Author's Latest Posts


Embedded Multicore: Enablement Of Heterogeneous OSes And Mixed Criticality Systems


The implementation of multicore embedded systems is becoming increasingly common. The decision to realize a design using multiple processors may be influenced by a number of factors; broadly these are technical goals to attain, a time to market to achieve, and target design and production costs. Using multicore in a design requires a number of key decisions, which, as with most embedded systems... » read more

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs


Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an RTL-based hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent products. The focus is on the techniques and automation of... » read more

Implementing A Multi-Domain System


IoT systems are multi-domain designs that often require AMS, Digital, RF, photonics and MEMS elements within the system. Tanner EDA provides an integrated, top-down design flow for IoT design that supports all these design domains. Learn more about key solutions that the Tanner design flow offers for successful IoT system design and verification. To read more, click here. » read more

A Specification-Driven Methodology For The Design And Verification Of Reset Domain Crossing Logic


Reset architectures have increased in complexity along with SoC designs. Sadly, traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a three-step specification-driven methodology that provides a requirements-based approach for reset domain crossing design and verification. To ... » read more

Place And Route Made Easier And Faster


By Allan Crone A predictable trend in IC design is the ever-increasing size and complexity of designs while keeping the time allocated for the projects the same or shorter. Along with the tape-out pressure, organizations need to find cost savings everywhere possible. Lowering the overall cost of ownership of EDA tools is a viable way to manage the design budget. Consequently, design teams ar... » read more

Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps


This paper uses examples and case studies to demonstrate how to leverage UPF 3.0 information model TCL query functions (aka Tcl Apps) and tool provided CLI commands to do low-power checking of a design. This is an innovative way to dynamically verify the low-power intent after simulation has completed and all waveforms are available. The paper also explains how users can write their own checker... » read more

Improve Volume Scan Diagnosis Throughput 10X With Dynamic Partitioning


Performing volume scan diagnosis on today’s large, advanced node designs puts demands on turn-around-time and compute resources. This paper describes a new technique to maximize diagnosis throughput while performing ever more demanding scan diagnosis. The dynamic partitioning technology in Tessent Diagnosis enables in a 50% reduction in scan diagnosis time using only 20% of the typical memory... » read more

Creating A Unified Platform For Automotive Embedded Application Development


Automotive embedded software complexity is ballooning as software applications play a critical role in delivering the features and functionality demanded in modern vehicles. Current software development methodologies are incapable of managing the numerous and intricate cyber-physical interfaces in the cars of today. To compete, companies must evolve their software development processes to estab... » read more

Improving Verification Predictability And Efficiency Using Big Data


By providing a Big Data infrastructure, with state of the art technologies, within the verification environment, the combination of all verification metrics allows all resources to be used as efficiently as possible and enables process improvements using predictive analysis. This paper covers the technology, the metrics, and the process, and it will explore a number of techniques enabled by suc... » read more

Reusable UPF: Transitioning From RTL To Gate Level Verification


This paper highlights the differences between an RTL UPF and a Gate Level Simulation UPF, and presents a new methodology to write RTL UPF in such a way that minimal changes are required during gate-level power verification. To read more, click here. » read more

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