An Integrated Approach To Power Domain And Clock Domain Crossing Verification

How to lower power with minimal impact on performance.


Reducing power consumption is essential for both mobile and data center applications. The challenge is to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power control logic, it does not validate the impact of power logic on multi-clock logic. This paper explains the new low power CDC issues and the CDC verification techniques developed to verify low power designs.

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