Author's Latest Posts


Addressing IC Reliability Issues Using Eldo


Advanced, short-geometry CMOS processes are subject to aging that causes major reliability issues that degrade the performance of integrated circuits (ICs) over time. Degradation effects causing aging are hot carrier injection (HCI) and negative bias temperature instability (NBTI), in addition to positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). Below ... » read more

IC Design: Preparing For The Next Node


The challenges of preparing for the next process node require constant preparation by the foundries, the EDA industry, and the design companies. Learn how Mentor works to prepare the Calibre nmPlatform for each “next node,” and ensure that its customers have the tools and performance they need to succeed. To read more, click here. » read more

Finding Code Problems Before High-Level Synthesis


In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology. But, it is extremely important that the high-level C++ model is correct. In addition, the C++ language has ambiguities that can be tough to catch during simulation. Even if correctly written, the high-level model could be cod... » read more

AI Chip DFT Techniques For Aggressive Time-To-Market


AI chips have aggressive time-to-market goals. Designers can shave significant time off of DFT and silicon bring up using the techniques described in this paper. Leading AI semiconductor companies have already had success with Tessent DFT tools. To read more, click here. » read more

What Is Generative Design And Why Do You Need It?


The automotive industry is undergoing an electronic revolution. As design complexity increases, the legacy methods and tools used by OEMs are struggling to meet the demands of this new automotive landscape. Engineers are being asked to produce more sophisticated designs under a perfect storm of complexity, cost, and change management pressures. Generative design empowers automotive design teams... » read more

Formal Apps Take The Bias Out Off Functional Verification


The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis


Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to clos... » read more

ON Semiconductor Conquers Verification Challenges


Motor controller IC design for automotive applications, such as power mirror, seats, door locks, and door lift control, creates exceptional verification challenges. Particularly because these ICs must work for over 10 years and they live in harsh environments including -40° C to 150° C temperature ranges, voltages ranging from 7V to 40V, and potential electrostatic discharge and electromagnet... » read more

Smoke Testing A High-Level Synthesis Design


Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after High-Level Synthesis (HLS), teams need a way to quickly ensure that the newly-generated RTL is functionally the same as the original untimed C++. They don’t want to create an RTL testbench in order to make this comparison. What teams need is an automated smoke test to quickly make the... » read more

Low Power Apps: Shaping The Future Of Low Power Verification


This paper describes how verification and design engineers can make use of UPF 3.0 information model-based HDL and Tcl APIs to write useful low-power apps. We present low-power apps that can be used to solve complex verification issues and provide case studies and examples to demonstrate usage. To read more, click here. » read more

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