How to significantly reduce power in chips with embedded SRAM.
The use of embedded static random access memory (eSRAM) in complex ICs has significantly increased in the past three decades. This trend will continue with the growth of ICs designed for rapidly expanding markets such as automotive, virtual reality (VR) / augmented reality (AR), implantable medical devices, gaming, sensor hub, medical devices, wearable computing, data center, and artificial intelligence (AI) applications.
The coolSRAM-6T offer breakthrough design characteristics which provides new opportunities for optimization of “novel ICs” in above applications, especially achieving the lowest power dissipation for strong product differentiation. Simultaneously, designers can benefit from coolSRAM-6T to address speed, area/cost consideration. coolSRAM-6T also greatly complements Mentor’s coolSRAM-1T, coolREG-6T, coolREG-8T, coolCAM, and coolROM.
Download this new whitepaper to learn more about:
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
Pitches continue to decrease, but new tooling and technologies are required.
Buried features and re-entrant geometries drive application-specific metrology solutions.
Issues involving design, manufacturing, packaging, and observability all need to be solved before this approach goes mainstream for many applications.
Global chip sales slump deepens; chipmakers’ data leakage issues; silicon wafer sales down; electronic system design sales up; Techcet wins CHIPS Act contract; Infineon breaks ground on German fab; new research center for SiC; winners of MITRE’s eCTF contest; new biosensing devices.
Existing tools can be used for RISC-V, but they may not be the most effective or efficient. What else is needed?
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Technical and business challenges persist, but momentum is building.
Gate-all-around is set to replace finFET, but it brings its own set of challenges and unknowns.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
High speed and low heat make this technology essential, but it’s extremely complex and talent is hard to find and train.
The industry seems to think it is a real goal for the open instruction set architecture.
Leave a Reply