A Hierarchical Instruction Cache Tailored To Ultra-Low-Power Tightly-Coupled Processor Clusters

A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves Technologies. Abstract: "High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) ha... » read more

SB MOSFET-Based Ultra-Low Power Real-Time Neurons for Neuromorphic Computing (Indian Institute of Technology)

A technical paper titled “Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing” was published by researchers at the Indian Institute of Technology (IIT) Bombay. Abstract: "Energy-efficient real-time synapses and neurons are essential to enable large-scale neuromorphic computing. In this paper, we propose and demonstrate the Schottky-Barrier MOSFE... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training

A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

New Way To Control Spin Currents At Room Temperature

New technical paper titled "Spin manipulation by giant valley-Zeeman spin-orbit field in atom-thick WSe2." from researchers at Beihang University (China) and University of British Columbia. Abstract: "The phenomenon originating from spin–orbit coupling provides energy-efficient strategies for spin manipulation and device applications. The broken inversion symmetry interface and the result... » read more

Always-On, Ultra-Low-Power Design Gains Traction

A surge of electronic devices powered by batteries, combined with ever-increasing demand for more features, intelligence, and performance, is putting a premium on chip designs that require much lower power. This is especially true for always-on circuits, which are being added into AR/VR, automotive applications with over-the-air updates, security cameras, drones, and robotics. Also known as ... » read more

Wavelength Multiplexed Ultralow-Power Photonic Edge Computing

Abstract "Advances in deep neural networks (DNNs) are transforming science and technology. However, the increasing computational demands of the most powerful DNNs limit deployment on low-power devices, such as smartphones and sensors -- and this trend is accelerated by the simultaneous move towards Internet-of-Things (IoT) devices. Numerous efforts are underway to lower power consumption, but ... » read more

Always-On DSPs

There are tradeoffs between powering circuits down to save power and waking them up to respond to voice and visual commands. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the best ways to deploy digital signal processors, why multiple DSPs are often better than just one, and what penalties there are for various approaches. » read more

Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

Abstract: "This paper presents a novel spiking neural network (SNN) classifier architecture for enabling always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual wake-up, in ultra-low-power internet-of-things (IoT) devices. Such always-on hardware tends to dominate the power efficiency of an IoT device and therefore it is paramount to minimize its power diss... » read more

An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks

Abstract:  "The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without clock architecture, with co-lo... » read more

← Older posts