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Verification Methodologies

A standardized way to verify integrated circuit designs.
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Description

A methodology defines the models that are created, how they are used and the ways in which tools are used to manipulate them. Models can define the design at several levels of abstraction, they can define the requirements of the design or they can define closure criteria.

The main purpose of a methodology is to optimize some aspect of the design while minimizing the time spent on it. It also ensures consistency within a company such that reuse becomes possible.

Over the years, companies have released numerous different methodologies using different languages.