Knowledge Center
Knowledge Center

Logic Simulation

A simulator is a software process used to execute a model of hardware


Logic simulators primarily work on register transfer level (RTL) models of the digital portions of a hardware system written in either the Verilog or VHDL languages. Most simulators are capable of accepting models in several levels of abstraction including gate, RTL and behavioral but are restricted to the semantics provided by the languages that they support. Commercial simulators often accept multiple languages in a single simulation meaning that the semantics of the various languages can be combined although restrictions are placed as to where the boundaries between the languages can reside.
The most prevalent technology used to build a logic simulator is called event driven. Events are created within the simulator whenever a signal changes value. These events are scheduled to happen at some point in the future based on the timing of the circuitry. The simulator ensures that events are handled at the correct time. Multiple events can happen at the same time and this is used to simulate the concurrency found within hardware systems. Simulation time is advanced when all events at the current time have been executed.

An extension of this technology is called compiled code simulation. A traditional event based simulator interprets the model to create the necessary events. A compiled code simulator will take portions of the RTL model and convert them into C code. These are then compiled and executed directly when the inputs to the RTL code segment change. The evaluation of that RTL block does not use the scheduling or other timing capabilities in the core simulator.

Another simulation technology that has been used in the past is called cycle simulation. This assumes that there are no timing issues within a design and that all events created within the circuit will have settled before the next edge of the clock. The simulator thus does not have to deal with timing, but on the downside, all pieces of the design are evaluated every cycle because it does not keep track of which pieces of logic change on each cycle. Few commercial simulators exist that use this technology today although this is the basis for most logic emulators. Emulators perform a similar task to simulation but using special purpose hardware instead of a generic computer.


Formal Signoff


Formal Datapath Verification