Beyond Signoff

To deal with increased variability at advanced nodes, new methodologies are needed.


The future of connectivity is very promising – the new era of semiconductors will give rise to transformational products that will enable seamless connectivity with 5G, smarter devices with AI, next generation mobility with autonomous vehicles and immersive experiences with AR and VR. These cutting-edge electronics systems will require the use of advanced sub-16nm SoCs and complex packaging technologies to deliver the required performance, functionality, and a rich user experience.

Increasing variability
Technology scaling has enabled greater performance, lower power and greater functional integration while driving down the cost of semiconductor chips over the years. However, for advanced sub-16nm process nodes, the economic benefits of transistor scaling are slowly diminishing. Tighter design schedules and margins, along with greater design size and complexity, are posing significant challenges for designers to achieve the desired power, performance and area targets.

Today’s advanced 16nm/7nm SoCs are challenged with increased variation effects as they push for lower power. While the sizes of the transistors continue to shrink following Moore’s Law, the threshold voltages fail to continue to scale. The lower power levels reduce the power profile but result in the transistors operating at near threshold voltage. This causes wide timing variability leading to difficulty in timing closure, design re-spins and poor functional yield. Variability has become the new enemy at advanced technology nodes. You can’t fix what you can’t find. Variability takes many forms. For instance, there is variability in process due to smaller geometries, variability in voltage drop due to varying workloads and variability in temperature across the chip due to increased self-heating and joule heating effects – and it directly impacts silicon performance. Increased cross coupling of various multiphysics effects such as timing, power and thermal in sub-16nm designs poses significant challenges for design closure. Power grid design and the profound impact of grid weakness issues on timing-critical paths have become limiting factors for achieving the desired performance and area targets. Power grid consumes a significant amount of metallization resources, and with routability now a big constraint at advanced nodes, power and timing closure have become a designer’s nightmare.

Margin-based methodologies under threat
Traditional margin-based methodologies that have served well in the past are becoming ineffective. These methodologies helped in confining the problem space by decoupling design methodologies to manage complexity and limitations in EDA tools that are not architected to solve multi-dimensional optimization problems. At advanced FinFET nodes, however, these siloed methodologies are increasingly failing to achieve the highest performance in silicon. Margins work well only as long as the results are predictable. With the margin-based approach, increased variability makes it hard to predict true silicon behavior and impacts both time to result (TTR) and time to market (TTM) goals in complex design projects.

Traditional signoff methodologies are very reactive, and simulation is considered the end game today. However, it should be pervasive and be a part of the game. For simulation to be part of the engineering loop, it has to be fast. Simulation should help designers build chips – correct by construction. It’s not sufficient for simulation tools to deliver just performance and capacity, which are meaningless when you are staring at 50,000 ECO fixes in the final stages before tapeout with a limited set of engineering resources to fix them. How would you figure out what exact fix needs to go into which block before tapeout? Simulations should have the ability to predict issues as the design evolves and help prioritize design issues, so that by the end of the design process when you reach signoff you are already in a good place to meet the time to market window with increased confidence for product success in the field.

Figure 1: ANSYS RedHawk-SC Accelerating SoC Power Integrity and Reliability Signoff

Simulation of advanced sub-16nm SoCs generates astronomical amounts of data. Traditional EDA solutions lack the ability to digest this vast amount of data, let alone provide any meaningful insights. Engineers need to be able to ask interesting questions that lead them to performing more meaningful analyses to help them design better to achieve superior yield, higher performance, lower cost – with the most optimum metallization and decap resources – and so on. The holy grail lies in the ability to leverage data to make decisions. Data is power, so it is important to make your data actionable and gain a competitive edge.

More than Moore challenges ahead
In addition, advanced packaging technologies will be the key driver of heterogeneous integrations in next generation HPC, cloud computing and automotive electronics systems to achieve extreme performance, high system bandwidth, low power and all this at a low cost. The internet of everything – the reality of tomorrow – will generate huge amounts of data to be processed and stored and the ability to handle such large volumes of data will be threatened by limited system bandwidth between the traditionally packaged processor and the memory that is integrated into the system. Hence, advanced 2.5DIC/3DIC packaging technology, including Through Silicon Vias (TSVs), die and wafer stacking, system-in-package (SiP), package-on-package (PoP), advanced wafer-level packages (WLP), and interposer integration that leverages the third dimension for scaling, will become a popular choice. Short interconnection paths enabled by TSVs between stacked chips lead to higher performance because of increased I/O speed; they also offer lower power due to reduced capacitance, and smaller form factor due to stacking multiple die. This is indeed a very promising technology, although it is fraught with many challenges due its complexity.

Figure 2: 2.5D/3DIC Setup for Chip Level Power/Thermal Integrity Analysis

Visit ANSYS@DAC to learn how ANSYS is empowering customers beyond signoff by bringing the power of multiphysics simulations, big data analytics and chip-package-system (CPS) co-analyses to exceed power, performance, area and reliability goals by breaking down margin barriers.

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