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Reliability Verification

Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.


Reliability verification is a category of physical verification that helps ensure the robustness of a design by considering the context of schematic and layout information to perform user-definable checks against various electrical and physical design rules that reduce susceptibility to premature or catastrophic electrical failures, usually over time.
Reliability is a growing concern for integrated circuit (IC) designers, especially in products such as communications, medical, and transportation, where reliability and performance are not just market differentiators, but critical aspects of safe and effective operation. Many reliability checks are difficult or simply not possible to check using traditional design rule checking (DRC), layout vs. schematic (LVS) and electrical rule checking (ERC) tools, and can potentially affect a wide range of IC designs. Electrostatic discharge (ESD), electrical overstress (EOS), Voltage-Aware DRC and latch-up are just some of the application areas that require these complex geometrical and electrical checks which can result in reduced device lifetime, reliability, yield, defect escapes to customers, and delayed failures in the field.

Contrary to traditional electrical checks using a single device/pin to net relation, reliability requirements can often only be described by a topological view that combines both circuit description and physical devices. Consequently, a reliability verification tool must have the ability to use both netlist and layout information to perform electrical checks that consider the context of the design intent for both layout-related and circuit-dependent checks. Such tools can also employ topological constraints to verify that the correct structures are in place wherever circuit design rules require them. Ideally, the tool can identify the complex circuit topology on a design netlist, either streamed from the schematic or extracted from the layout. Once topologies of interest are identified, the tool typically checks the specific constraints, usually defined by the design team, whether they are electrical or geometrical. Topology recognition capabilities can also be employed to quickly check specific sections of designs rather than the entire chip. The programmability aspect enables the design team to augmented standard foundry rule decks to include custom verification requirements based on design rules for circuit reliability.

Low-power and multiple-power verification requires system knowledge and careful tracking of signals which cross power domains. Some reliability verification tools employ static voltage checking to propagate expected voltages throughout the design based on the input voltages on IO pins. These rules can be used to propagate voltages across different device types to identify signal lines crossing from one domain to another without appropriate design protection structures in place (like level shifters). The verification of these multiple power domain configurations and others enable verification of the layout or the schematic for early detection of scenarios which would lead to premature silicon failure.

ESD checks typically include several considerations, such as identifying possible areas of electrical failure, geometrical constraints of device dimensions, the number of device fingers, distance from supply pads, and different circuitry requirements for multiple power domains. When given the appropriate design parameters, a reliability verification tool can identify the circuit elements that make up ESD protection structures and ensure that they have the correct values, that elements are properly connected with respect to the core IC, and that no elements are missing.

Reliability verification often considers the transistor placement and design interactions, which can have a significant impact on design robustness. Such interactions include:
• Point-to-Point resistance (P2P)
• Current Density (CD)
• Voltage-Aware DRC, to avoid time dependent dielectric breakdown (TDDB)
• Hot gate/diffusion identification
• Layer extension/coverage
• Device matching

Identifying areas of weakness in both pre- and post-layout verification environments is an important aspect of reliability verification. While there are many tools capable of performing one specific aspect of reliability verification (P2P or CD only, or topology only checks, for example), understanding the design in context, while incorporating verification for both topological and layout considerations is of paramount importance for a comprehensive reliability verification solution capable of considering all aspects of this type of verification in a single platform.

Original page contents provided by Mentor Graphics


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Planning Out Verification

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