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Languages are used to create models


Languages in EDA (electronic design automation) are used for modeling. A language normally has one or more models of computation that supply the semantics that go along with the language. For example, Verilog implies the way in which a simulator executes the language, although in some cases Verilog semantics are ambiguous. This has created problems within a flow where simulation and synthesis semantics inferred from the language are different. The semantics define an event driven system based on fine grained concurrency with gate level timing.

Semantics are presented by syntax. Some languages have several syntaxes that go along with them. For example the Property Specification Language (PSL) has various flavors that are in the Verilog, VHDL and SystemC syntax. In all cases the semantics of the language are the same.

Another attribute of a language are the abstractions that they can represent. A language may be restricted to a single abstraction, but it is more common that a language can express multiple abstractions. For example, Verilog can describe systems at the register transfer level, or at a behavioral level. Other languages such as C are able to express higher-level constructs than Verilog, and yet the semantics of C are those of a sequential stream of instruction, or in other words, a processor is the implied execution vehicle.

Different points in a design and verification flow favor different languages. At the Electronic System Level (ESL) the most popular language is SystemC. SystemC is built on top of C and C++ and adds some concepts necessary to model hardware, such as concurrency. Other languages as being used such as Bluespec, OpenCL and MATLAB/Simulink.

At the Register Transfer Level (RTL) the most popular language is Verilog, which has now evolved into SystemVerilog. The “system” moniker is a misnomer as it is not highly suitable for describing systems. VHDL was a major contender and is still in use in certain geographic domains and application areas. It also has a lot more popularity for FPGA-based designs.

SystemVerilog is the primary language used for verification, although the main competitor is still home grown testbenches written in C. The e language was also a contender and is still being actively supported by Cadence. PSL is a language used for defining properties.

Analog and mixed-signal design primarily uses SPICE for the most accurate models and various abstractions have been created as extensions to Verilog and VHDL. Recently a mixed-signal set of extensions has been standardized for SystemC and work is underway to extend SystemVerilog into this domain as well.

Non executable languages also exist. The Unified Power Format (UPF) defines power intent and SystemVerilog and e also contain coverage models that are used to track verification completeness. IP-XACT is a meta-data language that helps tools assemble systems out of IP blocks.

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