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Transistors

Basic building block for both analog and digital integrated circuits.
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Description

The transistor is the basic building block for both analog and digital circuits. Made out of semiconductor material, the transistor is a small device that amplifies, controls, or switches electrical signals. Each transistor has three leads, called the emitter (source), the collector (drain), and the base (gate).

Transistors can be broken into two main categories — planar and 3D.

The first transistors were invented in 1948 by Bell Labs as a way to improve the vacuum tube amplifiers used in telephone and early computer systems. In 1958, the first integrated circuits were invented. (See the Computer History Museum for more info about the invention of the transistor and integrated circuits.) The transistor went from a discrete device — which are still used today — to being something etched onto an integrated circuit. Today, advanced chips have billions of transistors etched onto them.

In a bipolar junction transistor (BJT) has either an NPN or a PNP configuration. In NPN, the P is the base and the Ns are the emitter and collector. In the PNP configuration, the N is the base and the Ps are the emitter and collectors.

In a field-effect transistor (FET), a voltage is applied to the gate, which creates an electric field that changes the current between the source and drain. FETs were first designed as planar, where the gate controls from one side. With trench FETs, the gate controls the channel from three sides. The main two types of FETs are JFETs (junction field effect transistors) and MOSFETs (metal–oxide–semiconductor field-effect transistors).

Fig. 2: Planar vs. trench MOSFET die layers. Source: Infineon

Fig. 1: Planar vs. trench MOSFET die layers. Source: Infineon

When a MOSFET turns on, the gate capacitor applies an electric field to the channel, creating an inversion layer. This allows minority carriers (holes in pFETs, electrons in nFETs) to flow between the source and the drain. When the transistor is off there is no capacitance: the energy barriers between the source, drain, and channel prevent current flow. As transistors shrink, the electric field density needed to create the inversion layer increases, and so the gate capacitance must increase. Up to a point, this is accomplished by reducing the thickness of the gate dielectric. As the gate dielectric thickness falls to only a few nanometers, however, quantum mechanical effects allow carriers to tunnel through it, increasing gate leakage and ultimately shorting the transistor.

Silicon transistors already have confronted this issue, which led to the introduction of high-k gate dielectric materials. As the dielectric constant (k) increases, the same capacitance is achieved with a thicker physical layer. Designers can minimize leakage while getting the electrostatic control they need.

In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond.

The industry has been exploring a number of next-generation transistor candidates. At 7nm, for example, the leading contender is the high-mobility finFET, which makes use of III-V materials in the channels to boost the mobilities. The electron mobilities for today’s silicon-based finFETs degrade at 7nm. Germanium (Ge) and III-V materials have higher electron transport capabilities, allowing for faster switching speeds. The first III-V finFETs will likely consist of Ge in the PFET, according to experts. Then, the next-generation III-V finFETs may consist of Ge for PFET and indium gallium arsenide (InGaAs) for NFET.

At 5nm, two technologies — gate-all-around field-effect transistor and tunnel field-effect transistor (TFET) — are taking a narrow lead. Considered the ultimate CMOS device in terms of electrostatics, gate-all-around is a device in which a gate is placed on all four sides of the channel. The gate controls the channel from all four sides. In contrast, TFETs are steep sub-threshold slope transistors aimed at low-power applications.

 

Fig. 2: CFET architecture. Source: Coventor, a Lam Research Company

Fig. 2: CFET architecture. Source: Coventor, a Lam Research Company

 

Fig. 3: Planar transistors vs. finFETs vs. gate-all-around Source: Lam Research

Fig. 1: Comparison of finFET and gate-all-around with nanosheets. Source: Lam Research

Fig. 4: Comparison of finFET and gate-all-around with nanosheets. Source: Lam Research

 

 

Fig. 4: FeFETs implemented on planar (left), finFET (center), and gate-all-around (right) structures. Source: FMC

Fig. 5: FeFETs implemented on planar (left), finFET (center), and gate-all-around (right) structures. Source: FMC

 

Fig. 1: N and P-type forksheet FET pair (left) and stacked nanosheet FET (right). Source: imec

Fig. 6: N and P-type forksheet FET pair (left) and stacked nanosheet FET (right). Source: imec

Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes.