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Taming Non-Predictable Systems


How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

What Happened To Execute-in-Place?


Executing code directly from non-volatile memory, where it is stored, greatly simplifies compute architectures — especially for simple embedded devices like microcontrollers (MCUs). However, the divergence of memory and logic processes has made that nearly impossible today. The term “execute-in-place,” or ”XIP,” originated with the embedded NOR memory in MCUs that made XIP viable. ... » read more

Last-Level Cache


Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

AI, Performance, Power, Safety Shine Spotlight On Last-Level Cache


Memory limitations to performance, always important in modern systems, have become an especially significant concern in automotive safety-critical applications making use of AI methods. On one hand, detecting and reporting a potential collision or other safety problem has to be very fast. Any corrective action is constrained by physics and has to be taken well in advance to avoid the problem. ... » read more

CodaCache: Helping to Break the Memory Wall


As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data ... » read more

Network Storage Optimization In Chip Design


Prathna Sekar, technical account manager at ClioSoft, explains how to manage large quantities of data, how this can quickly spin out of control as colleagues check in data during the design process, and how to reduce the amount that needs to be stored. » read more

The New CXL Standard


Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Machine Learning Inferencing At The Edge


Ian Bratt, fellow in Arm's machine learning group, talks about why machine learning inferencing at the edge is so difficult, what are the tradeoffs, how to optimize data movement, how to accelerate that movement, and how it differs from developing other types of processors. » read more

Meltdown, Spectre And Foreshadow


Ben Levine, senior director of product management for Rambus’ Security Division, talks with Semiconductor Engineering about hardware-specific attacks, why they are so dangerous, and how they work. » read more

Edge Inferencing Challenges


Geoff Tate, CEO of Flex Logix, talks about balancing different variables to improve performance and reduce power at the lowest cost possible in order to do inferencing in edge devices. https://youtu.be/1BTxwew--5U » read more

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