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Shift Left

In semiconductor development flow, tasks once performed sequentially must now be done concurrently.


The term “Shift Left” has been used increasingly within the semiconductor development flow to indicate tasks that were once performed sequentially must now be done concurrently. This is usually due to a tightening of dependences between tasks.

Perhaps the first and biggest example of Shift Left happened with logic synthesis. Originally, it was responsible for taking a design, written in Verilog at what is called the Register Transfer Level (RTL) and transforming the design into a netlist of gates. Those gates would then go through a place and route tool to create the physical layout of the chip. Logic synthesis assumed that the majority of the delays in a path were associated with the logic gates and that wire delay could be ignored. As chip geometries became smaller, gate delays went down and wire delays increased. It became increasingly difficult to close timing and the iteration loop between place and route and logic synthesis was not controllable. It thus became imperative that logic synthesis and place and route were essentially done at the same time. Physical design was shifted left and became a part of logic synthesis. Timing closure has now become a lot more predictable.

Today, there is a general goal to analyze all aspects of a system at the earliest possible place in the development flow. This reduces the potential for surprises later on, which tend to be more expensive and more difficult to correct.

Another example of Shift Left is the desire to be able to run software on the hardware as soon as possible. Traditionally, teams would have to wait for first silicon to become available before any hardware/software integration can be performed. Thus, if problems were found, the only place to fix them was in the software–often resulting is highly suboptimal solutions. Today, teams use virtual prototypes, emulators and physical prototypes as early platforms on which software can be executed.The virtual prototype is generally available very early in product development, long before RTL exists, but does not have accurate timing. When RTL is available, that can be mapped into an emulator and this provides the first accurate model of the hardware. However, if higher execution speed is required, a physical prototype, often utilizing FPGAs becomes necessary. In each progression from virtual prototype to physical prototype, the iteration time becomes longer and thus only used as the design begins to stabilize.


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