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DFT For SoCs Is Last, First, And Everywhere In Between

A new approach to DFT insertion that supports accurate, early verification and seamless handoff to downstream synthesis.

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Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free.

Fast forward to today and things have changed quite a bit. There is still the mandate to verify functionality and screen for defects, but the path to get there is now more complex. Design complexity has increased substantially along with more sophisticated test approaches. Design for test (DFT) is now a well-defined discipline to address testability of complex SoCs. Early DFT insertion at the RTL phase of design allows early verification, but this approach can be inefficient in optimizing power, performance and area. Late DFT insertion will be more efficient but will delay verification and thus push out the schedule. These forces present something of a Ying and Yang for DFT. Let’s examine these opposing forces to see why DFT for SoCs needs to be considered first, last, and everywhere in between.

Ying – Functional validation of DFT

This is a story of complexity management. Large designs require sophisticated and similarly large test strategies. Some examples of this growing DFT complexity include:

  • Hierarchical testing of cores and subsystems
  • Scan compression
  • Logic built-in self-test (LBIST)
  • Memory built-in self-test (MBIST)
  • Boundary scan, driven by the IEEE 1149.1, test access port (TAP) consisting of data, control signals, and a controller with sixteen states
  • IEEE 1500-compliant core wrappers
  • EEE 1687-based access networks (aka iJTAG)
  • On-chip clock controllers

To facilitate early validation, DFT can be implemented at the RTL phase of design. This enables validation and easy debug of the interaction of the DFT logic, typically with Verilog simulation which is much more efficient than gate-level validation. The result is a significant increase in productivity, but non-optimal PPA since RTL DFT does not contain physical guidance for synthesis.

Yang – Optimal PPA

Just as design techniques have expanded to support a wide pallet of DFT options, synthesis tools, such as Design Compiler NXT and Fusion Compiler have also expanded to support the physical insertion of these technologies. This DFT implementation approach easily accommodates many designs, and leveraging synthesis technology, ensures optimal PPA.

The problem occurs because it potentially delays verification until a gate-level netlist with all DFT structures inserted is available. This will slow the design project down. The figure below illustrates this challenge.

The answer – Shift-left verification

Addressing the DFT Ying/Yang problem requires a new approach to DFT insertion and verification. One that supports accurate, early verification of major DFT components at RTL and seamless handoff to downstream synthesis and lower-level DFT implementation. The result is early verification of the complete design, allowing downstream DFT tasks (ordered scan chains, core wrappers, physical congestion optimization of compression, test points, etc.) to seamlessly blend with the complete flow. This approach is called shift-left and is illustrated in the figure below.

The Synopsys TestMAX family of products delivers a complete solution to implement a shift-left DFT verification and implementation flow. The result is both early verification and optimal PPA for complex designs with complex DFT approaches. Key features of the TestMAX family include:

  • Early analysis of testability at RTL
  • Core wrapping with shared use of existing core registers near core I/Os
  • High scan compression with congestion optimization
  • Automated MBIST insertion
  • Ordering of scan chain elements based on location
  • Location-based connection of test points
  • Location-based grouping of SE pipelining with flops

For your next design, consider DFT first, last and everywhere in between to solve the DFT Ying/Yang problem.



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