Author's Latest Posts


Making IC Test Faster And More Accessible: Part 1


The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

Building Bridges: A New DFT Paradigm


Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today (think smartphones, laptops, televisions, etc.) contain hundreds to thousands of interconnected scan chains used to verify that the semiconductors were manufactured without defects. Because the imp... » read more