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RTL Signoff

A series of requirements that must be met before moving past the RTL phase


Register Transfer Level (RTL) Signoff is a series of well-defined requirements that must be met during the RTL phase of IC design and verification before moving on to the next phase. The next phase is typically synthesis, followed by place & route. The justification for RTL Signoff is to make sure that the right verification, checks, and fixes, are performed on the RTL, as early as possible in the flow, rather than waiting until they are found during the latter stages, resulting in costly rework.

RTL Signoff flow encourages local iteration rather than more costly iterations caused by problems found later in the flow

Some examples of RTL Signoff requirements include:

  • Lint clean for simulation and synthesis
  • Code and functional coverage goals met, including assertions
  • Clock and reset domains verified, through static and dynamic verification
  • Timing constraints (SDC) verified, including false and multi-cycle paths
  • Detection and removal of X-propagation sources
  • Stuck-at and at-speed coverage goals met
  • Power goals met, including power estimation and reduction
  • Power and voltage domain verification
  • Power intent (UPF) verification
  • Area, timing, and congestion analysis to ensure physical clean RTL

Since the turn of the century, there has been a significant increase in design complexity resulting from the integration of multiple functions on a single chip. Increasing reliance on externally sourced semiconductor Intellectual Property (IP) content, both from third-party IP suppliers and from other design groups within the same company, has impeded the quality assurance process.

It is a significant task to ensure that all SoC functions work together seamlessly, that the device can be manufactured reliably, is cost effective, has enough battery life, and responds to every command in a timely manner. The problem is further compounded by increasingly short market windows and shrinking product cycles for most products. The need to manage this risk is driving an increased reliance on IP reuse. Using proven IP reduces design risk, but still leaves risk in assembly and “spec” compliance. IP reuse methodologies are not yet plug-and-play and IPs are open to bugs, misuse, abuse, and surprises when used outside tested configurations.

RTL Signoff Addresses Challenges Of SoC Design
RTL Signoff reduces risk:

  1. RTL provides enough detail to detect and fix significant problems in a timely manner along with the appropriate attention from the knowledgeable design engineers, compared to larger amounts of data to sift through and the cursory design knowledge from the implementation engineers post synthesis and layout.
  2. RTL tools run faster and are less expensive than synthesis and layout tools, which allows the designer, most familiar with the design, to find and fix problems at RTL more quickly than could be done post synthesis or layout.
  3. Higher quality RTL reduces the risk of expensive iterations from synthesis or layout back to RTL – A restart of synthesis or design layout is quite costly in engineering time and tool runtime.

RTL Signoff can be applied effectively to both internal and 3rd party IP (IP Signoff):

  1. Since most IP is sourced as RTL, signoff checks can be enforced as part of handoff requirements from the IP supplier, and as acceptance checks by the SoC integration team.
  2. When dealing with configurable IP, there is no guarantee the configuration in which a designer wants to use the IP in the SoC has been thoroughly validated by the supplier.

IP Signoff enables efficiencies for SoC level RTL Signoff (SoC Signoff):

  1. At the SoC level, the integrator must validate assumptions in the IP and make necessary adjustments when the two are not in sync.
  2. Once validated, the SoC-level signoff can focus on IP integration and commonplace issues at this higher level.

SoC Signoff provides additional efficiencies:

  1. With IP Signoff, it is not necessary to validate the internals of IP at the SoC integration stage, as long as IP validation models can be intelligently abstracted.
  2. Abstraction can drive an order of magnitude improvement in analysis time while reducing computing hardware requirements.
  3. Ultimately, this leads to a significantly simplified flow.

Slight variations of RTL Signoff are also defined for FPGA designs.

Historical Perspective
The meaning of RTL Signoff has changed since it was first coined around the year 2000. At that point, RTL Signoff meant that the RTL code or a synthesized netlist could be handed off to an ASIC vendor or the fab, without the RTL designer having to be further involved. It was the ASIC vendor’s task to drive the physical implementation and ensure that the design met its goals for performance, power, area, testability, etc. However, a modern SoC design no longer offers that luxury because of sheer size, complexity, and stringent requirements. The RTL designer must take an active role to ensure that the design is ready for implementation by driving a complete RTL Signoff flow.

Page contents originally provided by Atrenta


Formal Signoff


Tech Talk: 7/5/3nm Signoff


Tech Talk: 7nm Power


Tech Talk: Power Signoff


Executive Briefing: Prakash Narain


RTL Signoff

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