tag: CDC

Ensure Zero Functional CDC Signoff Defects With VC SpyGlass Integrated Solution
By Synopsys - 06 Mar, 2024 - Comments: 0

This whitepaper will explain how designers can ensure zero defects seamlessly using Synopsys VC SpyGlass as a single cockpit for not just structural CDC analysis but also for complete functional analysis. We will also cover how designers can utilize a single dashboard for tracking the functional CDC signoff progress over the course of the project. Click here to read more. » read more

Accellera Preps New Standard For Clock-Domain Crossing
By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

Achieve 10X Faster CDC Debug Leveraging Machine Learning
By Synopsys - 25 Jan, 2023 - Comments: 0

Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of asynchronous clock and reset domains is growing heavily within these complex SoCs, leading to millions of clock domain crossing (CDC) violations at the SoC level. Each of these violations ... » read more

Formal Verification Ensures The Perseverance Rover Lands Safely On Mars
By Joseph Hupcey III - 28 Apr, 2022 - Comments: 0

By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

Achieving CDC Signoff On Multi Billion Gate Designs With Hierarchical CDC Flow
By Synopsys - 06 Jul, 2021 - Comments: 0

For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC ... » read more

An Integrated Approach To Power Domain And CDC Verification
By Kurt Takara - 11 Mar, 2021 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power... » read more

Taming Non-Predictable Systems
By Brian Bailey - 28 Jan, 2021 - Comments: 0

How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

Systematic Methodology To Solve Reset Challenges In Automotive SoCs
By Mentor, a Siemens Business - 02 Dec, 2020 - Comments: 0

Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

Multi-Mode Clock Domain Crossing Verification Enables Analysis Efficiency And Accuracy
By Mentor, a Siemens Business - 29 Jul, 2020 - Comments: 0

This paper shows how automated modal CDC analysis is used to exhaustively verify CDC issues in all test and operational modes of an SoC with multiple IPs. This new approach automatically consolidates all results from each mode, making issues very easy to interpret and debug. What took days and weeks with the prior manual approach now takes only a few hours. To read more, click here. » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy