VC SpyGlass’ hierarchical CDC signoff methodology to verifies clock domain crossing problems at the SoC level.
For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC matches its design specification. The verification cycle can be reduced drastically by ensuring functionality of IPs that can be achieved by verification at the IP level. Once IPs are qualified as per design specifications, then SoC logic and IPs interfaces can be verified to ensure that there is no metastability, convergence, coherency etc.
Synopsys next-generation VC SpyGlass RTL signoff platform has the capability to extract IP level interface information that can be plugged-in at the SoC level to verify inter-block crossings, convergence and glitch prune logic to meet design specifications. This white paper talks about VC SpyGlass’ hierarchical CDC signoff methodology to verify clock domain crossing problems at the SoC level.
Author: Navneet Chaurasia, Sr Applications Engineer, Synopsys
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