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Achieving CDC Signoff On Multi Billion Gate Designs With Hierarchical CDC Flow


For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC ... » read more

An Integrated Approach To Power Domain And CDC Verification


Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power... » read more

Taming Non-Predictable Systems


How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision makers invariably decide that some degree of uncertainty is warranted. Understanding uncertainty is at least the first step to making informed decisions, but new tooling is required to assess the im... » read more

Systematic Methodology To Solve Reset Challenges In Automotive SoCs


Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

Multi-Mode Clock Domain Crossing Verification Enables Analysis Efficiency And Accuracy


This paper shows how automated modal CDC analysis is used to exhaustively verify CDC issues in all test and operational modes of an SoC with multiple IPs. This new approach automatically consolidates all results from each mode, making issues very easy to interpret and debug. What took days and weeks with the prior manual approach now takes only a few hours. To read more, click here. » read more

Maximizing Value Post-Moore’s Law


When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Eliminate Silicon Respins With Netlist CDC Verification


Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for... » read more

Constraint-Based Verification Of Clock Domain Crossings


There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impa... » read more

Manufacturing Bits: March 9


Finding cures for coronavirus The Department of Energy’s Oak Ridge National Laboratory (ORNL) is using the world’s most powerful supercomputer to identify drug compounds and cures for the coronavirus. [caption id="attachment_24162601" align="alignleft" width="300"] Summit supercomputer. Source: Oak Ridge National Laboratory[/caption] The supercomputer, called Summit, has identified 7... » read more

An Industry Under Siege


The coronavirus is taking a big toll on the semiconductor industry's unquenchable thirst for new information. The longer it lasts, the more the industry will have to resort to technology — some new, some old — to continue moving forward. Over the past couple weeks, conferences and trade shows have been postponed or outright canceled. Synopsys, Cadence and Intel pulled out of DVCon at the... » read more

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