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Achieving CDC Signoff On Multi Billion Gate Designs With Hierarchical CDC Flow


For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC ... » read more

Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff


By Himanshu Bhatt and Paras Mal Jain Detecting and debugging deep sequential CDC convergences using structural CDC verification is extremely difficult since doing a flat analysis on large designs has capacity related challenges, and even if verification tools can complete the analysis, it becomes a nightmare to debug the violations with complex sequential logic. Thus arises the need for dyna... » read more

Security And Convergence


I’ve had a lot on my mind the past few weeks while reporting on seemingly disparate topics like the Internet of Things, embedded software and hardware accelerators, but in the world today, these things are really tightly connected, actually. They all boil down to convergence and security in my mind. Looking at the Internet of Things (IoT), which promises to connect all of us and all of our... » read more