tag: DFT

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test
By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Observability Is Essential For Modern Silicon
By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

AI Accelerator Testing Depends On DFT Innovations
By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield
By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Enhancing Silicon Reliability With In-System Test And SLM Data
By Adam Cron - 07 Apr, 2026 - Comments: 0

Innovation in semiconductor development and manufacturing shows no signs of slowing down. Ever-larger chips at ever-smaller geometries create new challenges all the time. At the same time, competitive pressures are shrinking time to market (TTM) and putting enormous pressure on project teams. Furthermore, the wide use of electronics in safety-critical applications demands better reliability, av... » read more

AI Accelerators Usher In New Era For IC Test
By Laura Peters - 07 Apr, 2026 - Comments: 0

Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

Analog Scan: Unlocking A New Era In Mixed-Signal Test
By Vladimir Zivkovic - 10 Mar, 2026 - Comments: 0

Anyone involved in IC product sign-off that includes a mixed signal design portion knows that developing robust tests for these intricate designs has historically been a significant bottleneck, no matter the application. It's a hurdle many of us have faced, leading to extended development times, high costs, and sometimes an unsettling uncertainty about the true quality of our tests. Traditio... » read more

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

Are You Using Structural Patterns In An SLT Environment?
By Peter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

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