tag: DFT

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

Are You Using Structural Patterns In An SLT Environment?
By Peter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

Chiplets Add More Inspection And Test Steps
By Anne Meixner - 10 Feb, 2026 - Comments: 0

Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier
By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

Scalable End-To-End Test Solutions For Today’s Complex SoCs
By Srikanth Venkat Raman - 17 Dec, 2025 - Comments: 0

By Srikanth Venkat Raman and Sri Ganta Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test costs, test quality, yield, debug, and turn-around-times. Scalable and efficient end-to-end test solutions that scale to large and complex SoC design cores... » read more

Tackling Chip Complexity With Integrated System-Level Test Solutions
By Davette Berry - 09 Dec, 2025 - Comments: 0

As the sophistication of semiconductors continues to grow, so does the need for system-level test (SLT) in production to ensure that high-performance processors, chiplets, and other advanced devices function as expected in real-world environments. Once seen primarily as a fallback to catch what traditional automated test equipment (ATE) missed, SLT has now become a mission-critical step for val... » read more

The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures
By Ann Mutschler - 25 Nov, 2025 - Comments: 0

Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, under... » read more

Chiplet Integration and Testing: Key Lessons for Next-Gen Semiconductor Packaging
By Vineet Pancholi - 20 Nov, 2025 - Comments: 0

The Chiplet Era Has Arrived The floodgates for chiplet-based design have officially opened. Over the past several quarters, manufacturing test flows have been validating 2.5D package architectures, and production volumes are ramping up. These designs promise flexibility and performance, but they also introduce new test sensitivities—electrical, thermal, and mechanical—that challenge tradit... » read more

Integrating Design Verification To Approach Zero Defects
By Jyothy Jaganathan - 06 Nov, 2025 - Comments: 0

As semiconductor applications in automotive, data center, and high-performance computing grow increasingly mission-critical, the industry faces mounting pressure to achieve near-perfect manufacturing test coverage—often exceeding 99%. Yet, meeting stringent zero-defect defective parts per million (DPPM) targets remains a formidable challenge. Traditional structural testing methods frequently ... » read more

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