Are You Using Structural Patterns In An SLT Environment?

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many benefits, which include lower cost of test because of its ability to test many devices in parallel, and SLT equipment has substantial memory capacity, which is ideal for managing larger and more complex pattern sets. Incorporating SLT into your high-volume manufacturing plans provides the opportunity to enter the market with the highest test coverage—and therefore the highest‑quality silicon—ensuring extended product reliability throughout its lifecycle.

Historically, when the Design-for-Test (DFT) engineers of the world hear system engineers talk about SLT, it’s time for coffee and “let’s see what free food is in the break room.” System-level test and DFT aren’t in the same conversation, right?

Nope, not anymore! Starting last year, Tessent In-System Test brought the DFT engineer back into the conference room and into the conversation by enabling structural pattern delivery in an SLT environment. In addition to supporting the classic in-field periodic testing to monitor silicon health, Tessent In-System Test now also supports scan pattern delivery using PCIe and USB interfaces from an external host. PCIe and USB interfaces are quickly becoming common on most commercial chips to enable data transfer on and off the chip at higher clock frequencies and data rates. Because they are capable of high-bandwidth data transfers, both PCIe and USB interfaces can be found on commercial and in-house SLT test equipment.

Fig. 1: Tessent In-System Test Controller used for structural pattern delivery using PCIe or USB.

The fundamental piece of hardware that is needed to use PCIe and USB interface for scan pattern delivery is the Tessent In-System Test Controller (ISTC). The Tessent ISTC is inserted into the SoC during DFT insertion and is physically placed between the HSIO interface and the scan-testable logic. The Tessent ISTC converts Advanced eXtensible Interface (AXI) read and write transactions to JTAG scan loads and Streaming Scan Network (SSN) streams. It is compatible with the full suite of industry-leading Tessent products including the diagnosis ecosystem and High-Bandwidth IJTAG.

Plan to test up to 100% of the testable logic in the SLT environment using higher‑quality Automatic Test Pattern Generation (ATPG) patterns than the traditional stuck‑at and transition‑delay ATPG patterns. Use patterns generated from expensive, high‑pattern‑volume fault models, including:

• timing‑aware fault models – ideal for detecting timing‑related defects in high‑performance silicon
• cell‑aware fault models – targeting intra‑cell defects that traditional gate‑level models miss
• stress‑test patterns – exposing reliability‑related weaknesses under extreme operating conditions
• multiple‑input‑switching patterns – identifying defects activated by complex switching activity within logic structures

Patterns created using these advanced fault models provide higher test coverage, improved defect detection, and higher‑yielding silicon, enabling teams to meet aggressive DPPM targets. These higher‑volume pattern sets are also far more manageable in an SLT environment, thanks to the large amounts of available pattern‑memory capacity that allow for efficient storage and delivery of complex test data.

Testing silicon in a System Level Test (SLT) environment is no longer optional—it’s a strategic requirement for achieving maximum product reliability and competitive advantage. As modern applications demand higher performance and longer in‑field lifetimes, integrating structural patterns and DFT methodologies into SLT becomes essential rather than separate disciplines. By embracing SLT using Tessent In-System Test as part of the overall test strategy, engineering teams can ensure their devices reach the market with:

• the highest possible test coverage
• reduced field failures
• stronger longer-term customer trust
• greater confidence in real-world reliability

Ultimately, SLT provides the most comprehensive opportunity to validate silicon performance under real‑world conditions, ensuring products remain robust, dependable, and ready to meet the demands of today’s evolving technology landscape.

Now is the time to evaluate your SLT strategy using Tessent In-System Test and ensure you’re leveraging structural test patterns to their fullest potential—your silicon’s long‑term reliability depends on it.