What’s required to improve the yield of multi-die assemblies.
Key Takeaways
The shift to multi-die assemblies is forcing changes in how chips are tested and inspected in order to achieve sufficient yield ramp or respond more quickly to yield excursions.
Assembly engineering teams have long relied upon optical inspection and electrical test to flag assembly manufacturing issues, but those approaches alone are no longer sufficient for chiplet-based designs. The number of sub-components to inspect and verify has more than tripled, and with each decrease in the pitch and size of balls, bumps, and microbumps, there are additional demands on metrology and inspection techniques.
To minimize the distances that signals need to travel in these devices, wafers and silicon interposers need to be thinned as well, which increases the risks of sub-surface and sidewall cracks. These subtle defects often escape inspection and electrical test, but they can kill a multi-die assembly in the field.
The good news is there are ways to minimize these issues. These include improvements in design for test (DFT) methodologies and performing multi-modal inspection/metrology as early in the assembly process as possible.
Fig. 1: Advanced packaging products include multiple components that benefit from metrology, inspection, and test. Source: Bryon Moyer/Semiconductor Engineering
What works, what doesn’t
The impact of multi-die is more screening steps to supplement existing approaches, and screening with more sensitivity and accuracy at each step. While automatic optical inspection (AOI) remains the workhorse for identifying the sources of yield loss in assembly and manufacturing, it can miss nearly imperceptible sidewall and subsurface cracks, as well as misalignments, voids, and head-in pillow bond issues.
“AOI remains relevant, but it fundamentally falls short in detecting hidden interconnects, subsurface voiding, and bond integrity issues, precisely the failure modes that are becoming more prevalent in advanced packaging,” said Vidya Vijay, senior product line manager for WaferSense & MRS at Nordson Test & Inspection. “Acoustic and X-ray inspection techniques can also be applied to assess die-to-die I/O connectivity, as well as the quality of wires, bumps, and interconnect structures.”
Metrology’s role likewise needs to expand. “Besides defect inspection with higher and higher sensitivity, various metrology capabilities are becoming more important,” said Monita Pau, senior director of product marketing at Onto Innovation. “These measurements can include critical dimensions of vias and RDL, as well as bump height, film thickness, RDL thickness, and via depth.”
Other changes are required, as well. In a manufacturing setting, electrical package test (ATE and system-level) is the last opportunity to detect failures and provide feedback on assembly process health. But that needs to be supplemented with on-die monitors, which can detect subtle variations and outliers in I/O circuit and interconnect performance.
“In practice, the most effective DFx strategy combines multiple approaches,” said Nir Sever, senior director of business development at proteanTecs. “Imaging and metrology catch gross defects and provide early process feedback. Embedded thermal and stress-related sensors add context and help localize root causes. High-resolution electrical monitoring of interconnects and logic paths closes the loop by showing whether assembly variation is actually eroding margin. Together, they provide actionable feedback to improve the assembly line, rather than isolated indicators that are difficult to interpret on their own.”
Process drift, defect excursions, and outlier performance need to be identified at each point in the manufacturing. This becomes more challenging in multi-die assemblies because feature parameters and defect mechanisms vary with each component. What doesn’t change is an engineering team’s need for early detection of issues.
Inspecting components, bumps and bonds
Accurate metrology and inspection measurements are essential for wafers, dies, interposers, and substrates. Those measurements provide relevant data to flag process drifts or defective components in advanced packaging processes.
AOI remains a foundational approach to detect the defects of interest and measures the critical parameters for RDL and bumps, but it continues to evolve to meet the accuracy and resolution needs of advanced packaging manufacturing. This includes higher measurement sensitivity and more inspection insertions.
“AOI is well-suited for detecting typical defects, including RDL and bump defects, such as opens, shorts, linewidth issues, missing or deformed bumps, and surface contamination,” said Onto’s Pau. “To catch issues earlier, manufacturers aren’t waiting for the completion of metallization steps for inspection. It is now typical for manufacturers to add inspection points throughout the buildup process (e.g. resist/dielectric lamination, after patterning and via formation). Traditional AOI benefits from new, novel inspection techniques for subsurface defects, low-contrast materials, and complex topography.”
Others concur on the continued value of optical measurements.
“AOI, leveraging both 2D and 3D imaging, is highly effective in detecting RDL defects, pad size variations, and bump quality issues such as diameter, height, and coplanarity, as well as missing or misaligned components, surface contamination, scratches, and cracks,” said Vijay. “With our multi-reflection suppression technology, defects on highly reflective bump surfaces can be reliably detected at sizes as small as 15 microns, with a technology roadmap extending to bump dimensions below 10 microns. AOI remains the fastest solution for 100% inline inspection in production, leveraging combined optical technologies with multi-angle imaging and AI defect classification to address increasingly smaller bumps and fine features.”
Fig. 2: Process flow for creating solder bumps and copper pillars. Source Bryon Moyer/Semiconductor Engineering
For process control, the solder metallurgy composition needs to be assessed. “Micro X-ray fluorescence (µXRF) is a natural technique to control the solder bumps composition (percentage of Ag in SnAg) and metal layers thickness (including Cu, Ti, Ni, Au). This is why it has been adopted for the in-line monitor of the above-mentioned parameters,” said Alexander Tokar, product marketing manager for µXRF/XRF at Bruker. “It is worth noting that the inline monitor started around 2006 and became increasingly critical with the decrease in bump diameters.”
Advanced packaging also adds a number of mechanical stresses, which result in more opportunities for crack defects.
“During the backside grinding and die sawing processes, cracks are the primary type of defects that can manifest,” said Nathan Peng, senior applications engineer at Onto Innovation. “These cracks occur due to the mechanical stress induced by the blade during die sawing or the grinder during backside grinding. Cracks can appear at the dicing street or the backside of the die, and can be classified as backside cracks, inner cracks, or hairline cracks based on their location and characteristics. Once generated, these cracks can propagate to the active die area, impacting individual die yield, or in severe cases, result in the breakage of the entire wafer. This is particularly critical for 2.5D advanced packaging, where singulated dies are attached to other devices through bonding processes. The pick-and-place and bonding processes introduce additional forces that may further compromise the integrity of the whole device.”
Optical detection for cracks is possible, but infrared and X-ray techniques provide higher sensitivity for detection with lower over rejection.
“X-ray topography (XRT) can be used to select known-good dies prior to bonding, ensuring that critical crystalline defects are not present, which could otherwise lead to later failures,” said John Wall, compound semiconductor business product manager at Bruker. “Additionally, XRT is employed for defect inspection in silicon interposers, which are prone to high breakage rates during assembly. Inspection is typically carried out early in the wafer or panel manufacturing process. These applications are currently in early-stage R&D and process development, with adoption expected to expand into high-volume manufacturing (HVM) in the future.”
Moving to longer wavelengths, infrared inspection can detect cracks. “Besides X-ray, IR is another technology that can see through layers to detect embedded defects,” said Onto’s Pau. “An application example is the use of IR to detect cracks on a chiplet after assembly.”
After singulation, detection of cracks in the range of 5 to 10 microns becomes challenging for optical techniques. Infrared inspection has greater sensitivity. With the latest detection components, in-line 100% inspections is now possible.
Fig. 3: Comparison of optical versus infrared detection capabilities for vertical microcracks. Source: Cohu
Detecting defects after the bonding step is naturally critical for chiplet-based products. And detection for process excursions can save hundreds of thousands of dollars. Engineering teams can use optical modalities to measure gross misalignments.
Fig. 4: Optical post-assembly measurements of interest. Source Nordson Test & Inspection
Acoustic techniques are becoming more relevant for assembly process control because it can ‘see’ through multiple layers. “SAM (scanning acoustic microscopy) is highly effective for detecting delamination, voids and cracking,” said Nordson’s Vijay. “Increasingly, metrology is no longer used solely as a pass/fail gate, but as a critical process control signal to monitor process steps and prevent escapes.”
Fig. 5: Acoustic imaging detection of delamination between die 2 and substrate in a stacked die. Source Nordson Test & Inspection
X-ray techniques excel at seeing between layers, which makes them well suited to assessing bonds after thermal compression bonding. X-ray equipment can be used during all forms of wafer-level packaging and can be trained to detect cold joints, head-in-pillow defects, misalignment, and missing features.
Another X-ray application is to detect for cracks post-bonding. As mechanically fragile components, thinned dies and wafers are susceptible to cracking from mechanical force applied during thermal compression bonding, which is anywhere from tens to thousands of newtons. “XRT is used during the wafer-to-wafer (W2W) and die-to-wafer (D2W) bonding processes to inspect for cracks and defects caused by bonding,” said Bruker’s Wall. “X-ray imaging can reveal internal crack propagation that is invisible externally. These cracks can lead to wafer breakage and device failure during subsequent packaging steps.”
Test and analytics
Electrical test after assembly provides data for process improvement. The ability to apply data analytics either at test for outlier detection, or connecting data across the assembly and test process, can pinpoint a specific cause.
But with electrical test separating out circuit failures from assembly, specific failures can be difficult to discern. The oldest standard, 1149.1 for PCB, supports point-to-point testing and only requires powering the boundary scan circuitry. In addition, this solution is I/O-agonistic. Such an approach in advanced packaging could be powerful as it could shift electrical identification of assembly defects further upstream.
“Not having a common standard for other interconnects is the problem, especially if there are logic dies sourced from different companies in the same package,” said Ken Lanier, principal technologist and director of strategic business development at Teradyne. “Additionally, UCIe and HBM interconnect testing requires powering up the entire chiplet and doing testing that requires reasonably sophisticated equipment. The potential benefit of boundary scan is that you may only need to power up the I/Os and run a very simple data sequence, eliminating many of the thermal and equipment complexity challenges. The hardware to do this type of testing would be small enough to put in-line with the packaging process to find failures immediately and drive corrective action before more defective devices are produced. One wrinkle with chiplets is whether the addition of this test capability would impact the performance of high-speed I/Os, which are optimized for lower power.”
Parametric performance of I/O and associated interconnect can detect subtle assembly defects that often escape inspection of microbumps, bumps, interconnects and bonds. Today, most interconnect standards for chiplet-based products enable on-die monitors to assess the electrical health of the point-to-point interconnect health by measuring timing and voltage margin in the data eye diagram. A single marginal lane can pass simple DFT-based tests and fail at time zero in a system, or fail after thermal cycling when a marginal bond becomes an open.
“Standard MBiST and protocol level tests are fundamentally pass/fail,” said Nir Sever, senior director of business development at proteanTecs. “They are very effective at catching gross faults, such as opens or complete shorts, but they are blind to marginal interconnect behavior. In HBM customer cases, issues were traced to post-assembly defects on the interposer that only manifested as reduced signal margin, not outright functional failure. Embedded interconnect monitoring exposed two dominant mechanisms. One was resistive bridging between adjacent lanes, which slightly degraded signal quality but still allowed MBiST to pass. The other was broader margin loss caused by die warpage and mechanical stress, which affected multiple neighboring lanes in a correlated way.”
To address a yield excursion, engineers need the appropriate data to identify the root cause. Throughout the manufacturing process, there are multiple sources of screening data, including inspection and electrical test. The detected signal can be 10 steps downstream of the process step causing the defects. Without connected data across the various chiplet assembly process steps, engineering teams have a nearly impossible task of finding the root cause so far upstream.
“The hardest part isn’t the inspection itself,” said Nordson’s Vijay. “It’s tying all the data together. Inspection, test, and tool data usually sit in different silos, often from different vendors. Connecting upstream process conditions to downstream electrical failures is still slow and very manual. That’s exactly why we provide optical, acoustic, and X-ray inspection solutions to give broader visibility across the process and to help close those gaps.”
Others agree on the lack of data sharing between test and assembly.
“In my work, I observe that our customers all have some level of traceability,” noted Dave Huntley, business development director at PDF Solutions. “They are tracing the most important and big chips, which use internal IDs. Their focus is typically straight from wafer sort to final test, i.e., correlating final test with wafer test and wafer fab data. But what they miss is all the assembly process data. With the complexities of advanced packaging, more defects occur during the assembly processes, and thus opportunities to improve an assembly process are hampered by not connecting test data with assembly process data.”
With more than 10,000 signals connecting chiplets, the spatial specificity of defective interconnect matters. Such data could connect defects to specific locations within the process tool environment, such as the corner of a die handler. “The value is not just in detecting that something went wrong,” said proteanTecs’ Sever. It’s also identifying why and where it went wrong. When you can see resistive behavior, spatial correlation across lanes, and margin degradation trends, you can turn unexpected failure rates into actionable process learnings instead of field escapes or costly over screening.”
Conclusion
With the increase in chiplet-based devices, factories are shifting from purely defect detection to process inference. This requires engineering teams to consider adding inspection insertions to facilitate earlier detection, enabling outlier detection with I/O parametric testing, and connecting all this data to assembly process information. Such investments will be driven by the costs associated with late detection.
“Test and inspection processes will evolve quickly, given the massive financial impact of multi-die packages that fail and cause the scrapping of a large quantity of good die because of silicon faults or sub-assembly issues not caught before the final assembly steps,” noted Teradyne’s Lanier. “Process control steps can be targeted with a good FMEA (failure mode and effects analysis) process, but many improvements will be driven empirically by what fails in later manufacturing steps or in the field.”
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