tag: semiconductor test

AI data Center Providers Seek Power and Bandwidth Promise in CPO
By Teradyne - 07 Apr, 2026 - Comments: 0

Co-packaged optics (CPO), a high-speed networking technology that integrates optical components (lasers, photodetectors) directly with switch/compute chips (ASICs) in the same package, continues to show promise. Advocates of CPO maintain that it reduces power consumption by over 80% and increases bandwidth density by shortening electrical traces to millimeters. Used primarily in data cente... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

AI Accelerators Usher In New Era For IC Test
By Laura Peters - 07 Apr, 2026 - Comments: 0

Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

Improving Yield Through Shared Data
By Ed Sperling - 11 Mar, 2026 - Comments: 0

Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

Chiplets Add More Inspection And Test Steps
By Anne Meixner - 10 Feb, 2026 - Comments: 0

Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Secure Data Sharing Becoming Critical For Chip Manufacturing
By Laura Peters - 13 Jan, 2026 - Comments: 0

Semiconductor companies increasingly need to share data to solve problems faster, boost yield, and trace the root cause of failed devices. But to make that work, companies need assurances that their data will be secure, free from data leaks that could result in the loss of valuable IP. Data sharing is becoming critical at leading device nodes, where process variability is starting to consume... » read more

Adaptive Test Gaining Ground For HPC And AI Chips
By Gregory Haley - 09 Dec, 2025 - Comments: 0

Adaptive test is starting to gain traction for high-performance computing and AI chips as test programs that rely on static limits and fixed test sequences reach their practical limits. The growing complexity of multi-die assemblies and power delivery, along with increased stresses, are forcing a shift toward real-time, data-driven optimization at the test cell. “It’s the same old pro... » read more

Challenges In Testing Photonics In Chips
By Ed Sperling - 21 Nov, 2025 - Comments: 0

The semiconductor industry has spent decades improving reliability and consistency by standardizing when and how to test it, how to collect critical data from those tests, and what to do with that data. But electrical test data is very different from silicon photonics, which is being bundled into these SoCs and multi-die assemblies alongside traditional electrical components. Aftkhar Aslam, CEO... » read more

Improving IC System Quality And Performance
By Ed Sperling - 12 Nov, 2025 - Comments: 0

Ensuring that multi-die assemblies and advanced SoCs will work as expected from time zero to the end of their lifecycle adds new challenges for chipmakers and their customers. Chips are being run harder, hotter, and for longer periods of time, often in unique configurations and with customized workloads. Alex Burlak, vice president of test and analytics at proteanTecs, talks about how to identi... » read more

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