tag: Bruker

Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging
By Anne Meixner - 07 Jul, 2026 - Comments: 0

Key Takeaways:  To support AI/HPC devices, high-density fan-out on panels must deliver increased RDL layer count and micropillar height while decreasing the trace and bump/micropillar pitch.   Metrology and inspection steps assist with achieving known-good panel requirements to avoid throwing away expensive chiplets, such as HBM and TPUs.  Optical measurement systems need to acco... » read more

When The Test Cell Lies
By Gregory Haley - 07 Jul, 2026 - Comments: 0

Key Takeaways:   A marginal test result can be electrically valid and still diagnostically misleading because the socket, load board, and thermal loop are now part of the measurement.   Separating device drift from test-cell drift depends on tracking margins, variance, and calibration trends rather than bins alone.   In advanced packages, a false pass destroys value downstream, ... » read more

Chip Industry Week In Review
By The SE Staff - 26 Jun, 2026 - Comments: 0

IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test
By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Chip Industry Week In Review
By The SE Staff - 05 Jun, 2026 - Comments: 0

Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Study of EUV Nanostructures Using AFM With High-Aspect Ratio Tip (Purdue, Intel, Bruker)
By Technical Paper Link - 11 Apr, 2026 - Comments: 0

A new technical paper, "Characterizing tip-sample interaction dynamics on extreme ultraviolet nanostructures using atomic force microscopy with a high-aspect ratio tip," was released by researchers at Purdue University, Intel Corporation and Bruker Corporation. Abstract "Accurate measurements of the nanometer scale geometry of extreme ultraviolet (EUV) lithography photoresist patterns are... » read more

Chip Industry Week In Review
By The SE Staff - 10 Apr, 2026 - Comments: 0

Deals, Funding Intel will join Elon Musk’s Terafab chip manufacturing project alongside Tesla, SpaceX, and xAI. Intel described its role as helping refactor silicon fab technology for a project targeting production of 1 TW/year of compute for AI and robotics applications. Intel and Google are expanding a multi-year collaboration on AI and cloud infrastructure, with Intel Xeon processo... » read more

What’s Failing At The Interface
By Gregory Haley - 07 Apr, 2026 - Comments: 0

Key Takeaways The interface is where failures in advanced packaging become visible, but it's increasingly not where they originate. Weak interfaces often don't fail at time zero, but they do degrade due to parametric drift and margin erosion that binary test screens miss entirely. The temporary test interconnect is the largest variable in the measurement chain and must be controlled ... » read more

Detecting Chemical Variability At Advanced Nodes
By Gregory Haley - 10 Mar, 2026 - Comments: 2

Key Takeaways Yield loss is increasingly driven by molecular variability in thin films, interfaces, and contamination rather than visible defects. Reliability issues often appear first as parametric drift or margin erosion under workload and thermal stress. Detection requires correlating molecular metrology, embedded electrical telemetry, and AI-driven wafer inspection. As s... » read more

Tool Matching Getting Tougher Across Test & Metrology
By Laura Peters - 10 Mar, 2026 - Comments: 0

Key Takeaways Engineers leverage both device-specific and tool-level data to identify a process "sweet spot." Tight, frequent tool-to-tool matching enables greater yield and fab flexibility. Machine learning helps capture the nuances of a tool's signature. Many people outside of the semiconductor industry wonder how humans can fabricate transistors with tens of nanometer sca... » read more

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