tag: Bruker

Chip Industry Technical Paper Roundup: July 1
By Linda Christensen - 01 Jul, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=426 /] Find more semiconductor research papers here. » read more

Viability of aZnMIm As A Resist For EUV Lithography (Johns Hopkins, Northwestern, Intel et al.)
By Technical Paper Link - 27 Jun, 2025 - Comments: 0

A new technical paper (preprint) titled "Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous Zeolitic Imidazolate Resists Deposited by Atomic/Molecular Layer Deposition" was published by researchers at Johns Hopkins University, Northwestern University, Intel Corporation, Bruker Nano, EUV Tech and Lawrence Berkeley National Lab. The paper states "This study demonstr... » read more

Chip Industry Week in Review
By The SE Staff - 27 Jun, 2025 - Comments: 0

AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Challenges In Using Sub-7nm ICs In Automotive
By Laura Peters - 10 Jun, 2025 - Comments: 0

The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge. Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over... » read more

E-Beam Inspection Proves Essential For Advanced Nodes
By Gregory Haley - 08 May, 2025 - Comments: 0

Electron-beam inspection is proving to be indispensable for finding critical defects at sub-5nm dimensions. The challenge now is how to speed up the process to make it economically palatable to fabs. E-beam inspection's notorious sensitivity-throughput tradeoff has made comprehensive defect coverage with e-beam at these advanced nodes especially problematic. For Intel’s 18A logic node (~1.... » read more

Atomic Force Microscopy: The Definitive AFM Modes Handbook
By Bruker - 08 May, 2025 - Comments: 0

This handbook illustrates the wide variety of operating modes available on Bruker AFMs, going well beyond the standard high‑resolution topographic imaging capabilities of AFM. The modes are broken into seven separate categories: morphology, electromagnetic properties, thermal properties, mechanical properties, chemical properties, electrochemical properties, and manipulation. Each category be... » read more

Why Thin Film Measurements Matter
By Laura Peters - 08 Apr, 2025 - Comments: 0

Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices. Whether it’s the read and writ... » read more

Nearly Invisible: Defect Detection Below 5nm
By Gregory Haley - 08 Apr, 2025 - Comments: 0

Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Hunting For Macro Defects
By Anne Meixner - 08 Apr, 2025 - Comments: 0

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the wafer level, a macro-defect can affect more than one die, and in some cases large regions of a wafer. Finding macro defects can indicate a significant issue with a process module, a particular fi... » read more

Automation And AI Improve Failure Analysis
By Laura Peters - 11 Mar, 2025 - Comments: 0

When a chip malfunctions it’s the job of the failure analysis engineer to determine how it failed or significantly deviated from its key performance metrics. The cost of failure in the field can be huge in terms of downtime, recalls, damage to a company’s reputation, and more. For these reasons, chipmakers take customer returns very seriously, focusing resources to quickly get to the bot... » read more

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