Speeding Up The R&D Metrology Process


Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times. The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generati... » read more

Metrology Challenges For Gate-All-Around


Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond


Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Week In Review: Manufacturing, Test


Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Inspection, Metrology Challenges Grow For SiC


Inspection and metrology are becoming more critical in the silicon carbide (SiC) industry amid a pressing need to find problematic defects in current and future SiC devices. Finding defects always has been a challenging task for SiC devices. But it’s becoming more imperative to find killer defects and reduce them as SiC device vendors begin to expand their production for the next wave of a... » read more

Week In Review: Manufacturing, Test


Public policy The rise of the digital economy is creating millions of new jobs, but it’s difficult to fill these positions. So, the Consumer Technology Association (CTA), a U.S.-based trade group, is encouraging hi-tech companies to offer more apprenticeships. This is especially true for software engineering, networking, data analytics, cybersecurity and artificial intelligence. The Semic... » read more

The Week In Review: Manufacturing


Trade The trade tensions are building between the U.S. and China. In the latest move, the U.S. Department of Commerce has imposed a ban on U.S. companies selling chips to ZTE, a Chinese telecom equipment and mobile phone vendor. The ban has been implemented on ZTE for seven years after the firm “was caught illegally shipping U.S. goods to Iran,” according to a report from Reuters. This ... » read more

Measuring FinFETs Will Get Harder


The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

Inside X-ray Metrology


Chipmakers are ramping up a new class of chip architectures, such as 3D NAND and finFETs. Measuring and characterizing the tiny structures in these technologies is a major challenge. It will not only take the traditional metrology tools, but also various X-ray techniques. To get a handle on X-ray metrology, Semiconductor Engineering recently discussed the trends with the following experts: ... » read more

The Week In Review: Manufacturing


Is the sky falling in the IC equipment market? Not yet, but watch out below. Semi capital spending is expected to reach $60.37 billion in 2015, down 1% from 2014, according to Pacific Crest Securities. “Although we trimmed 2016 capex three weeks ago, we are trimming some more. We now see semiconductor capex down 4% in 2016. However, we do not see capex falling off a cliff in 2016 (i.e., down ... » read more

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