AI Models Transform Defect Inspection And Review, But Can Fail To Scale


Key Takeaways: AI plays a role in improving defect capture rate and distinguishing between yield-killing and nuisance defects. New developments in wafer edge inspection are proving essential to bonded wafer yields. 70% of AI initiatives stall after pilot implementation, but some pitfalls can be avoided. One of the brightest spots in AI use today is the industry’s ability t... » read more

What I Learned At The 2026 GSA Tech Summit: The Future Of Semiconductor Collaboration Is Full Stack


I had the privilege of joining a panel at the Global Semiconductor Alliance (GSA) Tech Summit in June in Scottsdale, Arizona, titled "Collaboration Models That Actually Work." It was a fitting title for an event that brought together executives from across the semiconductor ecosystem, including foundries, fabless companies, equipment makers, EDA vendors, cloud providers, and systems integrat... » read more

2026 ASMC – Building the Core Pillars for AI in Semiconductors


Abstract: This presentation outlines a practical pathway for semiconductor manufacturers to move beyond AI experimentation and achieve scalable, value-driven implementation. As rising process complexity, massive data volumes, and talent constraints make AI a strategic necessity, this presentation highlights why over 70% of AI initiatives stall, primarily due to fragmented data, legacy system... » read more

What’s Really Needed For Advanced Test?


By Greg Prewitt and Marc Jacobs Advanced test has become one of the semiconductor industry's most promising frontiers: adaptive binning, feed-forward models, and real-time analytics pulling signals from mountains of measurement data. But there is a problem hiding underneath all that ambition, and it is neither compute nor algorithm; it is data. More specifically, it is the unglamorous, found... » read more

Smart Test Collides With The Data Chain


Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

Features And Benefits Of The SECS/GEM Standard – eBook


Discover how the SEMI E30 SECS/GEM standard empowers smarter, more efficient manufacturing by enabling factories to seamlessly collect equipment data, reduce integration costs, implement advanced process control, and improve overall operational performance. This eBook walks through key GEM capabilities—including collection events, alarms, recipe management, terminal services, and more—to s... » read more

Breaking The Legacy Trap: How Semiconductor Executives Can Accelerate AI Adoption And Transform IT Applications At The Same Time


The semiconductor industry is facing a strategic paradox. AI has rapidly moved from experimental technology to a competitive necessity promising faster yield improvement, smarter supply chain decisions, and autonomous factory operations. Yet the very systems that semiconductor manufacturers depend on to run their fabs, manage their supply chains, and serve their customers were built for a diffe... » read more

AI Accelerators Usher In New Era For IC Test


Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

Platform-Led AI Analytics for the Semiconductor Ecosystem


Abstract: Semiconductor manufacturers face a mounting data crisis: modern fabrication facilities generate petabytes of complex, siloed data, yet less than 5% of it is typically used in analytics. Traditional business intelligence tools lack the scalability to handle datasets with millions of parameters, leaving critical yield and quality insights untapped. In this presentation we outline a c... » read more

Challenges In Scaling Chips To 2nm And Below


Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

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