Some Chipmakers Sidestep Scaling, Others Hedge


The rising cost of developing chips at 7nm coupled with the reduced benefits of scaling have pried open the floodgates for a variety of options involving new materials, architectures and packaging that either were ignored or not fully developed in the past. Some of these approaches are closely tied to new markets, such as assisted and autonomous vehicles, robotics and 5G. Others involve new ... » read more

Week In Review: Manufacturing, Test


Trade SEMI has voiced support and encouragement for trade discussions between U.S. President Donald Trump and the People's Republic of China President Xi Jinping. The talks are planned for Dec. 1 during the G20 Summit in Argentina. SEMI expressed hope for a deal and offered principles beneficial to the microelectronics supply chain. Recent tariffs and trade tensions, on top of rumored expor... » read more

Carmakers To Chipmakers: Where’s The Data?


The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Variation At 10/7nm


Klaus Schuegraf, vice president of new products and solutions at PDF Solutions, explains why variability is a growing challenge at advanced nodes, why middle of line is now one of the big problem areas, and what happens when a via is misaligned due to a small process variation. https://youtu.be/jQfggOnxZJQ » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm


Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Design Compliant Source Mask Optimization (SMO)


Source Mask Optimization (SMO) is required to extend the use of 193 water immersion lithography to the 22nm technology node. Although SMO is being aggressively pushed in volume production the layout design implications of this technology have not been openly discussed. In this paper, the impact of layout design style on simultaneous SMO of Logic and SRAM is studied. In particular the improvemen... » read more

Week In Review: Manufacturing, Test


Chipmakers GlobalFoundries said that it is putting its 7nm finFET program on hold indefinitely and has dropped plans to pursue technology nodes beyond 7nm. To be sure, it was a tough decision by GF to put 7nm on hold. But generally, analysts believe that GF made the right decision. “There’s only a handful of semiconductor companies that will require high-volume 7nm technology right when... » read more

Week In Review: Manufacturing, Test


Trade wars The Trump administration unveiled a plan to impose additional tariffs on $200 billion of Chinese goods on July 10. The announced product list included more than ten categories of LED package and lighting products, according to LEDinside, a division of TrendForce. The export value of the major lighting products in the list reached $5 billion in 2017. “So far, the impact of the U... » read more

Week In Review: Manufacturing, Test


Chipmakers TSMC has reduced its outlook for 2018 revenue and capital spending, according to Bloomberg. The company blamed the outlook on sluggish “mobile and digital currency mining demand,” according to the report. Samsung has developed the industry’s first 10nm-class 8-gigabit LPDDR5 DRAM. The 8Gb LPDDR5 boasts a data rate of up to 6,400 megabits-per-second (Mb/s), which is 1.5 tim... » read more

Estimating MOSFET Leakage From Low-Cost, Low-Resolution Fast Parametric Test


A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient tran... » read more

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