tag: functional verification

Faster Bug Discovery And Coverage Closure
By Synopsys - 24 Nov, 2025 - Comments: 0

Modern chip development is a complex process where functional verification often consumes a significant portion of project time and resources. Achieving efficient bug discovery and coverage closure is essential to prevent issues from reaching silicon. This white paper introduces an innovative approach using AI-powered Verification Space Optimization (VSO.ai) to enhance verification processes. ... » read more

Verification Fails To Keep Up
By Brian Bailey - 28 Aug, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Streamlining Functional Verification For Multi-Die And Chiplet Designs
By Cadence - 30 Jul, 2025 - Comments: 0

An Opportunity and a Challenge The manufacturing aspects of multi-die/multi-chiplet designs are often highlighted, but what about verification? Functional correctness and performance of inter-die connections via a standard interface, such as UCIe or a custom inter-die interface, are not guaranteed to meet all system requirements. These interfaces must be verified comprehensively, ensuring co... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

First-Time Silicon Success Plummets
By Ed Sperling - 27 Mar, 2025 - Comments: 0

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both... » read more

Verification Tools Straining To Keep Up
By Brian Bailey - 01 Jul, 2024 - Comments: 0

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Accelerate Test Regressions with Synopsys VIP Using Dynamic Test Loading in VCS
By Synopsys - 27 Jun, 2024 - Comments: 0

Functional verification ensures that a design meets its specification requirements. The initial 80% of the verification process significantly impacts the time needed to complete the final 20%, which involves extensive test scenarios and regression testing, often consuming substantial engineering resources. Typically, the desired scenario emerges late in the test case, often in the last minutes ... » read more

Paradigms Of Large Language Model Applications In Functional Verification
By Siemens EDA - 03 Apr, 2024 - Comments: 0

This paper presents a comprehensive literature review for applying large language models (LLM) in multiple aspects of functional verification. Despite the promising advancements offered by this new technology, it is essential to be aware of the inherent limitations of LLMs, especially hallucination that may lead to incorrect predictions. To ensure the quality of LLM outputs, four safeguarding p... » read more

Generating And Evaluating HW Verification Assertions From Design Specifications Via Multi-LLMs
By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs” was published by researchers at Hong Kong University of Science and Technology. Abstract: "Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically describe... » read more

Glitch Power Issues Grow At Advanced Nodes
By Ann Mutschler - 11 Jan, 2024 - Comments: 0

An estimated 20% to 40% of total power is being wasted due to glitch in some of the most advanced and complex chip designs, and at this point there is no single best approach for how and when to address it, and mixed information about how effective those solutions can be. Glitch power is not a new phenomenon. DSP architects and design engineers are well-versed in the power wasted by long, sl... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy