Enabling full multi-die system functional verification and early testing long before interposer characteristics are pinned down, without requiring new test benches.
An Opportunity and a Challenge
The manufacturing aspects of multi-die/multi-chiplet designs are often highlighted, but what about verification? Functional correctness and performance of inter-die connections via a standard interface, such as UCIe or a custom inter-die interface, are not guaranteed to meet all system requirements. These interfaces must be verified comprehensively, ensuring coverage goals are achieved as the system evolves, as we demand for each component in a multi-die system.
Fig.1. New way to build a SoC. Source: Cadence.
However, this objective presents significant scaling challenges, as an integrated multi-die top-level must be created, debugged, and verified. The simulation size will be very large, which is not a problem for an emulation system such as Palladium or an FPGA-based prototyper such as Protium; however, those premium engines are likely to be assigned to mid- to late-stage large system verification, validation, and software bring up rather than at the earlier stages of the design cycle.
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