New Nonvolatile Memory Winners Emerge

Key Takeaways: 

• MRAM and RRAM will likely coexist, each with a different focus.
• PCRAM isn’t being ported onto finFET nodes.
• FeRAM is seeing new life, while a newcomer has a new NVM bit cell.

Newer nonvolatile memory (NVM) technologies are poised to take over from flash in embedded applications on newer process nodes. Magnetic RAM (MRAM) and resistive RAM (RRAM) appear to be the heirs apparent, leaving phase-change RAM (PCRAM) behind on older nodes.

Meanwhile, another company is developing a completely new bit cell — one that could even replace DRAM. And ferroelectric RAM (FeRAM) is still waiting in the wings.

RRAM and MRAM are likely to coexist, with the former featuring a lower cost, and the latter faster and better at handling extreme conditions. Both have an edge over embedded flash, especially on modern process nodes, but they won’t threaten standalone flash given NAND flash’s cost advantage. Any new bit cell, meanwhile, will take time to be accepted by the industry.

One of the factors motivating the consideration of non-flash technologies is that flash supply is increasingly limited, with prices heading way up. “HBM, DRAM, and NAND are all pushing to satisfy what feels like an insatiable amount of demand over the next couple of years,” said Sean Dougherty, vice president of sales at Everspin. “The big guys are literally committing their available volumes to a small number of players and decommitting from or exiting other industries.”

Three longstanding competitors
The three NVM technologies most visible over the last few years are MRAM, RRAM, and PCRAM. MRAM has existed for some time as a stand-alone memory, although for specialized applications. PCRAM technology was first employed on music CDs, but it’s having a harder time as a memory. RRAM is more novel, but gaining traction.

“MRAM is frequently positioned for higher-speed, higher-endurance embedded use cases such as persistent working memory,” said Suhail Zain, vice president of regional marketing at UMC.

RRAM, meanwhile, appears to be targeting a broader range of systems based on its favorable cost. “RRAM is commonly targeted for general-purpose embedded non-volatile memory adapted for applications such as firmware storage in IoT microcontrollers or configuration memory in a PMIC,” Zain said. 

Table 1: RRAM and MRAM characteristics, as built by UMC. Source: UMC

“Both MRAM and RRAM are gaining traction,” said Daryl Seitzer, principal product manager, embedded memories at Synopsys. “From a maturity perspective, MRAM is quite active. On the RRAM side, commercialization has been picking up. There’s embedded RRAM in microcontrollers coming from Nuvaton and Infineon.”

Despite years of work, PCRAM appears to be losing this race. No commercial offerings have appeared, and there appear to be no development efforts to port it to finFET nodes and beyond. Synopsys builds compilers for embedded memory, and could do so for PCRAM if there were customer interest. “There’s not been enough demand from any customer that says, ‘I want to be able to embed it, I want to be able to design it into my chip, and I need a compiler to do that,’” said Seitzer.

Others concur. “PCRAM is on the market in planar CMOS technologies,” said Robert Wiesner, distinguished engineer, technology concepts for embedded controllers at Infineon. “However, we don’t observe any activities to bring PCRAM to finFET nodes, while there are development activities for RRAM and MRAM.”

Scaling as an important factor
One of the main attributes boosting the fortunes of MRAM and RRAM is their ability to scale to new process nodes. Flash is fundamentally stuck at the 28nm node. It maintains its cost advantage through the 3D architecture, which keeps flash far cheaper than any other technology. Flash is so dominant that none of the new technologies aim to beat it at what it does best — standalone memory.

“Standalone flash has a strong cost advantage,” said Seitzer. “You’re not seeing a lot of pickup of RRAM or MRAM standalone chips.”

Although flash may have the advantage for standalone memory, the situation flips for embedded use. “The effort to integrate flash in state-of-the-art CMOS processes became a significant concern at 28nm and afterwards (e.g. finFET),” said Wiesner. “Process complexity has strongly increased, while the further shrink potential is stagnating.”

For this reason, MRAM and RRAM are widely seen as a boon for embedded memory. They require fewer additional steps than embedded flash and they offer byte addressability, which NAND flash lacks. NOR flash is byte-addressable and is more commonly used to hold code in MCUs. But if a monolithic MCU needs a finFET process, NOR flash is unavailable. This is where both MRAM and RRAM can play.

“A key advantage of both is that they can be implemented primarily in the back-end of semiconductor manufacturing, enabling relatively straightforward integration into existing logic platforms with a limited number of additional mask layers,” said Zain.

“Foundries like Samsung or TSMC or GlobalFoundries are offering embedded MRAM, as well as embedded RRAM,” said Sanjeev Aggarwal, Everspin’s CEO. “Customers are picking RRAM whenever they have a commercial application, and they’re picking MRAM where they care about performance and reliability, which is industrial and automotive.”

The foundries appear committed to these technologies. “Both RRAM and MRAM are on the roadmaps of the foundries for the long term — RRAM more on cost-optimized code flash replacements, while MRAM could be used with an SRAM-like flavor for data storage, as well (high endurance requirements),” said Wiesner.

Seitzer concurred. “The TSMC roadmap supports 12 and 6nm.”

Is SRAM a target?
Some folks are cheeky enough to try to replace SRAM simply because of SRAM’s impact on die size. “Embedded SRAM is not getting the density dive as you move forward with nodes,” said Dougherty. “Memory continues to dominate die size, which is very expensive.”

The closest folks come to that is the hope that an NVM technology can serve as a last-level cache. “MRAM read speeds aren’t quite as fast as SRAM,” said Jamie Schaeffer, vice president of product management at GlobalFoundries. “They’re not close to picosecond read speeds, but they’re close to 10 picosecond read access.”

Although MRAM’s and RRAM’s characteristics differ, their utility overlaps greatly. MRAM has found utility in space and automobiles, both of which are hostile environments. If tuned for speed, rather than data retention, it can be faster than RRAM. Target applications can be broad.

That said, manufacturing requirements are exacting. “The majority of emerging nonvolatile memory technologies can leverage existing semiconductor manufacturing infrastructure, but there are some unique integration challenges that push process requirements well beyond standard memory flows,” said Anish Khandekar, senior director of engineering, global products administration at Lam Research. “For example, MRAM patterning often requires ion-beam etch to precisely define magnetic stacks, since conventional plasma etch is not sufficient for these materials. At the same time, these devices are tightly constrained by back-end thermal budgets, driving the need for highly controlled low-temperature CVD and ALD processes. Materials challenges are also more demanding.”

MRAM has the speed advantage
MRAM has three fundamental technology versions. Toggle MRAM is the oldest, having been commercialized by Everspin as a standalone memory. The current version being commercialized is called spin-transfer torque (STT), and it has a smaller bit cell than toggle. Performance and endurance tend to compete, making this a technology that tends to get tuned for specific applications.

MRAM has fast read and write times and good endurance, so the toggle versions available today are largely employed for data logging, which requires constant writing. “There’s no need to wear level, there’s no need to pay attention to the external batteries or capacitors,” explained Dougherty.

“There’s a tradeoff between endurance and performance, but that is not necessarily a process difference,” said Seitzer. “It’s an implementation difference in how hard you’re pushing the write of the cell.”

The STT tradeoffs are being addressed by the third version, spin-orbit transfer (SOT). SOT is still in research and likely years from commercialization. “There’s no commercial offering out there that I’m aware of,” said Dougherty.

The key here is the best fit for a particular workload or application. “MRAM is a back-end memory, having among the fastest read/write speeds of non-volatile memories,” said Zain. “It is a great persistent working memory for applications where the operating environment is well controlled. This includes aerospace systems and automotive applications with shielded environments.”

Others agree. “We see MRAM fitting the automotive MCU space and industrial automation with difficult ambient requirements,” said Schaeffer.

“We believe that MRAM is going to play a significant contribution in edge AI,” said Dougherty. “The density and the read and write performance are much more important on those edge AI embedded systems.”

However, there appears to be disagreement over whether external magnetic fields are a real issue for MRAM. They could be for toggle versions, but they’re shipped in a shielded package. STT MRAM is naturally immune, according to Everspin, but rightly or wrongly, there still appears to be concern in the industry.

“For some applications the magnetic susceptibility of MRAM is a serious concern,” said Wiesner. “Magnetic field specs apply in the production flow and in the field.”

Everspin, the only provider of standalone MRAM, believes otherwise. “Our STT MRAM is magnetically immune just by the nature of the materials that we’re using,” said Aggarwal.

RRAM is cheaper
RRAM comes in two flavors. Conductive-bridge RAM (CBRAM) works by creating and destroying a metal filament through a dielectric barrier. OxRAM, by contrast, moves oxygen vacancies around in a dielectric. OxRAM appears to be winning this particular race, and it’s already being integrated into microcontrollers (MCUs).

“OxRAM tends to be favored for foundry-friendly, high-volume integration because its materials are based on metal oxides common in CMOS and inert electrodes, which can translate into cleaner back-end integration and lower contamination risk,” said Zain. “CBRAM relies on electrochemical movement of active metal ions to form and dissolve a conductive bridge. That mechanism can raise additional concerns around metal diffusion and contamination control, tight process windows, and reliability guard-banding in a logic fab environment.”

OxRAM is also seen as handling a wider range of environments than CBRAM. “OxRAM is positioned as stronger for high-temperature retention and robustness, since its switching is driven by oxygen-vacancy and filament modulation rather than repeated plating and stripping of a metal filament,” Zain said. “That makes OxRAM more attractive for use cases that demand long data retention at elevated temperatures and consistent behavior across a wide operating range.”

RRAM has fast read speeds, but OxRAM has a write challenge. “It’s almost as slow as flash, or maybe even slower in some cases,” said Aggarwal. “It doesn’t require the bulk erase, but it’s still very slow to write.”

On the plus side, RRAM has lower cost and a smaller footprint. “The main advantage I see is the simplicity of the RRAM technology process — a small capacitor (bottom electrode, dielectric, top electrode) in the BEOL stack, plus a select device in standard CMOS, no exotic materials, no special tools needed,” said Wiesner.

“RRAM is well suited for 300mm eNVM SoC platforms, including MCU-based applications, due to its strong compatibility with front-end CMOS processes,” said Zain. “This adaptability also makes RRAM attractive for integrating NVM into specialty processes, such as BCD [bipolar-CMOS-DMOS] and embedded high voltage [devices].”

Infineon has selected RRAM for MCUs on nodes beyond 28 nm. “The ATV [Infineon’s brand] RRAM version Infineon developed with TSMC fulfills all major requirements known from previous embedded flash technologies,” said Wiesner, citing data retention at over 1,000 hours at 175 °C (a high-stress temperature corresponding to around eight years at 125 °C and 200,000 years at 40 °C), 250,000 code changes, 15.2‑ns read times, an extended temperature range of -40 to 160 °C, and high quality levels.

Infineon found RRAM to be easier to build than MRAM, but the company also is looking at MRAM to replace SRAM when employed to store data.

One that’s quietly shipping
Ferroelectric RAM, or FeRAM, has been in development for years, and it’s actually in commercial production for very specific tasks. It relies on a dielectric that can take on two crystallization orientations as states. The dielectric is treated like a capacitor, which CEA-Leti calls a FeCap.

A big FeRAM benefit is very high endurance. “If you want to write information constantly and have it stored in a non-volatile way, FeRAM is very appealing,” said Laurent Grenouillet, integration and device engineer at CEA-Leti. “This is why it is used today in commercial products for datalogging.”

FeRAM also features low write power. “The beauty of ferroelectric memories is that you only need to apply voltage across the FeCap [with no appreciable current] to write the information,” said Grenouillet. “With resistive memories you need to pass current through the device, and this consumes typically 100× more energy.”

The big challenge with FeRAM as built today is scaling. “It has been commercialized for many years with PZT, but it’s not scalable, so they are currently limited at 130 nm,” said Grenouillet. “PZT is not CMOS compatible, and it cannot be deposited by atomic layer deposition [ALD].”

CEA-Leti recently reported that it had successfully implemented a FeRAM at 22nm using hafnium zirconium oxide (HZO) for the bit cell. HZO involves materials already widely employed in CMOS fabs and can be deposited using ALD. The group is now using a thin 7nm film and is working to scale it down to 5 or 4nm.

“Embedded FeRAM needs between two and four additional masks for integration,” said Grenouillet. “At 20 nm, it can be 2.5× smaller than SRAM.”

The capacitor is vertical, resembling the one used for DRAM (and even potentially a bit taller at 1µm). “The more FeCap area, the more margin you have for the memory window,” explained Grenouillet.

Micron did a project a couple of years ago that created a 32‑Gb FeRAM, which it called NVDRAM. Given its timing, which competes with standard DRAM, this was essentially a nonvolatile version. The company has yet to commercialize it, however, so it’s unclear whether some aspect rendered it unfit for production or whether this was simply a resource-priority decision.

A completely new bit cell
A new company called Quinas, meanwhile, has developed a completely new bit cell unlike any other NVM technology. It employs a floating gate, but the path for electrons to get there takes a novel path.

“UltraRAM is a compound-semiconductor floating-gate memory device — effectively a III‑V analog of flash memory — but with a fundamentally different charge transfer mechanism,” said James Ashford-Pook, CEO of Quinas. “Instead of tunneling through a dielectric oxide, it uses quantum resonant tunneling through engineered III‑V heterostructures.”

“On top we’ve got the floating gate, and below that we’ve got the channel that’s similar to flash,” said Peter Hodgson, CTO of Quinas. “In flash, you would have a dielectric region to block the charge and prevent it from leaking out of the floating gates. We’re taking advantage of quantum mechanics to make a region that is extremely resistive when there’s no voltage applied to the device, but as soon as we apply 2.5 V to it, we can get electrons resonantly tunneling up or down through this region.”

Quinas’ memory has three AlSb barriers that separate two InAs quantum wells. “These are designed and grown in such a way that the ground state energy levels of these two quantum wells are slightly misaligned at zero voltage,” Hodgson explained. “When no voltage is applied to the device, it’s impossible for the electrons to move from the channel to the floating gates or from the floating gate back to the channel.”

Fig. 1: Quinas’s UltraRAM cell. FG = floating gate; TBRT = triple-barrier resonant tunneling structure. This image shows how the bit cell is formed. Source: Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli, Richard Beanland, Manus Hayne, CC BY 4.0, via Wikimedia Commons 

The tunneling layers are extremely thin, with one consisting of only four monolayers and another of 17. At these dimensions, quantum effects dominate. “The electrons are in all these places at the same time, so the wave function basically stretches out through the structure,” said Hodgson.

The bit-cell materials aren’t considered friendly for a CMOS fab, so they’re building these in a III‑V fab instead. “The materials we’re using here are called the 6.1 angstrom family of semiconductors,” said Hodgson. “GaSb, InAs, and AlSb all have lattice constants very close to 6.1 Å. Silicon fabs don’t like these materials because they’re considered a contaminant, but they are very widely used in photodiodes, lasers, and opto-electronics.”

That poses a challenge for the control logic that must accompany the bit cells. Quinas sees two ways to approach this. One uses a separate silicon control chip, which is then bonded to the III‑V chip that holds the bit cells. The other is to develop logic circuits on a III‑V wafer.

The company claims extremely high data retention. As for endurance, the company found no degradation after 10 million cycles.

“We’ve got infinite retention time,” said Hodgson. “We didn’t want to say that in the paper because that may be a bit controversial. So instead, we drew a straight line, which is probably underestimating our retention, but it still goes to 10,000 years, which is more than enough for any memory.”

Data retention and endurance may be high due to a gentle programming approach as opposed to hot-carrier injection or Fowler-Nordheim tunneling. “The main reason for this, we think, is because we’re putting so little energy into the device, there’s no real reason for it to be damaged,” Hodgson explained.

Because this requires a III‑V foundry for the bit cell, volume could be limited by the capacity of such foundries. “We don’t see this as a fundamental limitation, although it is an important consideration in our manufacturing strategy,” said Ashford-Pook. “Our initial target markets are deliberately low-volume, high-value applications where energy efficiency, endurance, and persistence matter more than cost per bit.”

Performance that targets DRAM
Quinas is working with large test structures for now, so results won’t reflect the performance once scaled down to a production node. “If we scale down the devices, we predict that this will correspond to a 1-ns switching speed at 20nm, which is competitive with DRAM — and in fact may be a little bit faster than DRAM,” said Hodgson.

Quinas started by targeting DRAM, as did Micron with its FeRAM project. The read speeds are competitive, and it requires no refresh, making read effectively faster (since it doesn’t have to rewrite the bit) and it consumes less power than DRAM. The cell size is expected to be 6F2, so it also competes well on cost (until it goes down to 4F2).

But now the company is shifting gears a bit to explore neuromorphic computing. The bit cell should be able to handle multiple levels, potentially making in-memory computing (IMC) a possibility. It’s also at a lower volume for now, which allows Quinas to ramp up shipments more gently.

The industry is extraordinarily conservative when it comes to huge changes like this. The challenge is to convince everyone that this idea is solid and that all the potential gotchas have been worked through. While the bit cell undergoes validation, the company is working on the manufacturing flow and the overall memory architecture, including the accompanying digital control logic. Quinas expects to hit the market in 2029.

The memory space gets more complex
For years we’ve worked with three basic memory technologies: DRAM, flash, and SRAM. Other technologies existed, but they haven’t really vied for high-volume production. That’s changing.

MCUs featuring MRAM and RRAM are already appearing, adding two new flavors to high-volume production. You won’t find standalone versions of either, however. PCRAM, by contrast, is looking like it’ll be left behind.

FeRAM has been held up by a lack of process scalability, but that could be changing. And while FeRAM, as an NVM, has interesting potential, replacing DRAM with it opens a vast new market if the industry has the stomach for it.

As for Quinas, it calls its technology UltraRAM, and while it is targeting specialized applications to start with, it’s also seeing it as potentially a universal memory. It looks interesting in its early days, but much work remains. It will either be disappointing or a really big deal. We’ll know in a couple of years.

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