Will Your Chip’s Memory Work As Expected?


Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design


Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability across key applications such as mobile, IoT, AI, HPC, automotive, crypto, and networking. Why read this digest... » read more

Digital Memristor-Based PIM From A Device And Reliability View (Northwestern, Technion)


A new technical paper titled "A Comparative Study of Digital Memristor-Based Processing-In-Memory from a Device and Reliability Perspective" was published by researchers at Northwestern University and  Technion – Israel Institute of Technology. Abstract "As data-intensive applications increasingly strain conventional computing systems, processing-in-memory (PIM) has emerged as a promis... » read more

Emerging Synaptic Memory Technologies For Neuromorphic CIM Platforms (Tampere Univ.)


A new technical paper titled "Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware" was published by researchers at Tampere University. Abstract: "The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive... » read more

Emerging NVM: Review Of Emerging Memory Materials And Device Architectures


A new technical paper titled "Emerging Nonvolatile Memory Technologies in the Future of Microelectronics" was published by researchers at Texas A&M University, University of Massachusetts and USC. Abstract "Memory technologies are central to modern computing systems, performing essential functions that range from primary data storage to advanced tasks, such as in-memory computing for ... » read more

A Route For More Efficient SOT-MRAM Designs (NTU, TSMC)


A new technical paper titled "Efficient Magnetization Switching via Orbital-to-Spin Conversion in Cr/W-Based Heterostructures" by researchers at National Taiwan University and TSMC. Abstract "A highly efficient spin–orbit torque (SOT) switching mechanism is crucial for the realization of practical SOT magnetic random-access memory (MRAM). This study proposes a Cr/W-based spin current sour... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)


A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

Advancements in SOT-MRAM Device Development (imec)


A technical paper titled "Recent progress in spin-orbit torque magnetic random-access memory" was recently published by imec. Abstract "Spin-orbit torque magnetic random-access memory (SOT-MRAM) offers promise for fast operation and high endurance but faces challenges such as low switching current, reliable field free switching, and back-end of line manufacturing processes. We review rece... » read more

The Impact of Magnetic Fields On STT-MRAM Operations


A technical paper titled "Impact of external magnetic fields on STT-MRAM" was recently published by researchers at Univ. Grenoble Alpes, Everspin, GlobalFoundries, imec, et al. Abstract "This application note discusses the working principle of spin-transfer torque magnetoresistive random access memory (STT-MRAM) and the impact that magnetic fields can have on STT-MRAM operation. Sources of... » read more

Research Bits: Sept. 24


Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

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