tag: compute-in-memory

Inference Accelerator that Integrates Compute-in-Interconnect and Memory to Mitigate the Memory Wall (NUS)
By Technical Paper Link - 20 Jul, 2026 - Comments: 0

Researchers at the National University of Singapore published a technical paper titled “CIMERA: Compute-in-Interconnect and Memory with Reconfigurable Precision for LLM Inference.” Abstract Excerpt: “This paper presents CIMERA, a reconfigurable-precision LLM inference accelerator that integrates compute-in-interconnect and memory to mitigate the memory wall and enable precision-aware e... » read more

New Nonvolatile Memory Winners Emerge
By Bryon Moyer - 16 Jul, 2026 - Comments: 0

Key Takeaways:  MRAM and RRAM will likely coexist, each with a different focus. PCRAM isn’t being ported onto finFET nodes. FeRAM is seeing new life, while a newcomer has a new NVM bit cell. Newer nonvolatile memory (NVM) technologies are poised to take over from flash in embedded applications on newer process nodes. Magnetic RAM (MRAM) and resistive RAM (RRAM) appear to ... » read more

Open DRAM Model For PIM Analysis In 3D DRAM (Georgia Tech)
By Technical Paper Link - 12 Jul, 2026 - Comments: 0

Researchers from Georgia Institute of Technology published a technical paper titled “Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM.” Abstract Excerpt: “In this work, we present an “Open DRAM Model” that enables comprehensive circuit-level analysis of DRAM operations across multiple architectures, including conventional 6F2 BCAT, scaled 4F2 VCT, and monolit... » read more

Will Your Chip’s Memory Work As Expected?
By Ed Sperling - 22 Jun, 2026 - Comments: 0

Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

Research Bits: Apr. 21
By Jesse Allen - 21 Apr, 2026 - Comments: 0

Compute-in-memory state space models Researchers from the University of Michigan mapped complex state space models directly onto a compute-in-memory architecture in an example of hardware-software co-design for edge AI. "Compute-in-memory systems offer very high energy efficiency and throughput, but they are rigid and not optimal for convolution and transformer networks. In this study, we s... » read more

Research Bits: Apr. 14
By Jesse Allen - 14 Apr, 2026 - Comments: 0

Authentication for edge devices Researchers from the University of Hong Kong, Tsinghua University, and the Southern University of Science and Technology designed a privacy-preserving system for edge devices that combines physically unclonable functions and compute-in-memory. The Co-Located Authentication and Processing (CLAP) system integrates authentication and processing functions within ... » read more

Research Bits: Jan. 27
By Jesse Allen - 27 Jan, 2026 - Comments: 0

Analog in-memory compute Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory Computing (CL-IMC) chip to reduce data movement between memory and processor. The fully integrated analog accelerator uses two 64×64 arrays of programmable SRAM cells along with integrated components including operational amplifiers and analog-to-di... » read more

MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)
By Technical Paper Link - 26 Jan, 2026 - Comments: 0

A new technical titled "Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications" was published by researchers at Seoul National University. Abstract "This work presents, for the first time, an investigation of the impact of random phase distribution on ferroelectric (FE) tunnel field-effect transist... » read more

Oxides Bring Low Leakage Transistors To Leading-Edge Memories
By Katherine Derbyshire - 22 Jan, 2026 - Comments: 1

AI workloads need to position more memory that uses less power in ever-closer proximity to computational logic. That overriding imperative is driving new memory designs and new materials exploration across a wide range of applications, including cache memory, working memory, as well as a new category, non-volatile memory used for direct computation. The largest of these, by volume, is workin... » read more

Emerging Synaptic Memory Technologies For Neuromorphic CIM Platforms (Tampere Univ.)
By Technical Paper Link - 21 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware" was published by researchers at Tampere University. Abstract: "The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive... » read more

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