Research Bits: Apr. 21


Compute-in-memory state space models Researchers from the University of Michigan mapped complex state space models directly onto a compute-in-memory architecture in an example of hardware-software co-design for edge AI. "Compute-in-memory systems offer very high energy efficiency and throughput, but they are rigid and not optimal for convolution and transformer networks. In this study, we s... » read more

Research Bits: Apr. 14


Authentication for edge devices Researchers from the University of Hong Kong, Tsinghua University, and the Southern University of Science and Technology designed a privacy-preserving system for edge devices that combines physically unclonable functions and compute-in-memory. The Co-Located Authentication and Processing (CLAP) system integrates authentication and processing functions within ... » read more

Research Bits: Jan. 27


Analog in-memory compute Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory Computing (CL-IMC) chip to reduce data movement between memory and processor. The fully integrated analog accelerator uses two 64×64 arrays of programmable SRAM cells along with integrated components including operational amplifiers and analog-to-di... » read more

MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)


A new technical titled "Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications" was published by researchers at Seoul National University. Abstract "This work presents, for the first time, an investigation of the impact of random phase distribution on ferroelectric (FE) tunnel field-effect transist... » read more

Oxides Bring Low Leakage Transistors To Leading-Edge Memories


AI workloads need to position more memory that uses less power in ever-closer proximity to computational logic. That overriding imperative is driving new memory designs and new materials exploration across a wide range of applications, including cache memory, working memory, as well as a new category, non-volatile memory used for direct computation. The largest of these, by volume, is workin... » read more

Emerging Synaptic Memory Technologies For Neuromorphic CIM Platforms (Tampere Univ.)


A new technical paper titled "Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware" was published by researchers at Tampere University. Abstract: "The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive... » read more

KAN Acceleration: Algorithm Hardware Co-Design Approach (Georgia Tech, National Tsing Hua Univ., TSMC)


A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems" was published by researchers at Georgia Institute of Technology, National Tsing Hua University and TSMC. Abstract "Recent developments have introduced Kolmogorov-Arnold Networks (KAN), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)


A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

Memory Wall Problem Grows With LLMs


The growing imbalance between the amount of data that needs to be processed to train large language models (LLMs) and the inability to move that data back and forth fast enough between memories and processors has set off a massive global search for a better and more energy- and cost-efficient solution. Much of this is evident in the numbers. The GPU market is forecast to reach $190 billion in ... » read more

Power Delivery Challenges in 3D HI CIM Architectures for AI Accelerators (Georgia Tech)


A new technical paper titled "Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators" was published by researchers at Georgia Tech. Abstract: "3D heterogeneous integration (3D HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, ad... » read more

← Older posts