Toward Neuromorphic Designs

By Katherine Derbyshire - 25 Oct, 2017 - Comments: 1

Part one of this series considered the mechanisms of learning and memory in biological brains. Each neuron has many fibers, which connect to adjacent neurons at synapses. The concentration of ions such as potassium and calcium inside the cell is different from the concentration outside. The cellular membrane thus serves as a capacitor. When a stimulus is received, the neuron releases neur... » read more

What Happened To ReRAM?

By Mark LaPedus - 21 Sep, 2017 - Comments: 8

Resistive RAM (ReRAM), one of a handful of next-generation memories under development, is finally gaining traction after years of setbacks. Fujitsu and Panasonic are jointly ramping up a second-generation ReRAM device. In addition, Crossbar is sampling a 40nm ReRAM technology, which is being made on a foundry basis by China’s SMIC. And not to be outdone, TSMC and UMC recently put ReRAM on ... » read more

New Memories And Architectures Ahead

By Brian Bailey - 13 Feb, 2017 - Comments: 4

Memory dominates many SoCs, and it is rare to hear that a design contains too much memory. However, memories consume a significant percentage of system power, and while this may not be a critical problem for many systems, it is a bigger issue for Internet of Things ([getkc id="76" kc_name="IoT"]) edge devices where total energy consumption is very important. Memory demands are changing in al... » read more

How Small Will Transistors Go?

By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

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Toward Neuromorphic Designs

What Happened To ReRAM?

New Memories And Architectures Ahead

How Small Will Transistors Go?

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