How Small Will Transistors Go?

Leaders of Imec, Leti and SRC talk about what’s after 7nm, who will play there, and what the challenges will be.


By Mark LaPedus & Ed Sperling

There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion.

Semiconductor Engineering sat down with each of the leaders of three top research houses—Imec, Leti and Semiconductor Research Corp. (SRC)—to determine what’s next, how we will get there, and where the potential problems will be. What follows are excerpts of those conversations.

SE: How far will device scaling go and what will it look like?

Marie Semeria, CEO of Leti: We will push scaling as far as we can. We can push to 3nm. We have designs at 3nm. But it will be costly…There is a new platform for 5nm (CMOS). So for 10 years we have been working on nanowire. We believe that nanowire will be the first platform for CMOS development. We also pioneered FD-SOI technology and proved the scalability of that technology up to 7nm. It is important for companies to know that they can develop their products for many different nodes. 28nm FD-SOI is already under fabrication.

Luc Van den hove, president and CEO of Imec: Clearly, finFET is the dominant technology at 14nm and 10nm. It will most likely be extended to 7nm. But going beyond 7nm, it’s going be hard for a classical finFET. And so that’s where we see the horizontal nanowire coming in. It may look very complicated and it is difficult. But it’s not such a major deviation to extend a finFET to horizontal nanowire. This is because it starts from a finFET. Then, we do some tricks in order to make those wires in a finFET. It’s a natural evolution. I expect that this will indeed happen at 5nm. Of course, we have to be careful what we call 5nm. There is a lot of debate about that…And then, we’ll probably extend it to 3nm. The next node will be vertical nanowires. At certain dimensions, it may go below even 3nm. We have a path there. Then, I’ve shown this possibility of stacking vertical nanowires. We have a roadmap laid out for at least several more generations.

Ken Hansen, president and CEO of SRC: The clarity is there to 7nm. There is a lot of activity at 5nm. I am convinced that there will be a 5nm node that’s based on mostly traditional kinds of devices, notwithstanding a gate-all-around as opposed to a finFET or something like that. If you get 5nm, that leads to the next node, which is 3nm. 3nm is very sketchy at this point in time. You know as well as I do that 5nm doesn’t mean what one micron meant in the old days in terms of the dimensions. But you are getting down and working with individual atoms, or a very few number of atoms. This is very difficult to control. It requires new and different design techniques to be able to account for the variability. This is both locally and also on the macro level to control your timing between different circuit branches in a digital system. So, there is enough work going on at 5nm. There will be a solution there. Assuming we go to gate-all-around kinds of technologies, that will probably lead to a 3nm. Beyond that, it’s questionable what’s going to be there.

SE: Will it be economically feasible to move forward beyond 5nm?

Semeria: It’s always a question of the compromise between cost, performance and energy saving. But that’s the story of the semiconductor development. It’s a combination of the architecture, the transistor, the strain, and so on…Even now there are only really four companies working on finFET. Nanowire is just the next version of finFETs. You can use nanowires or nanosheets. It’s not so complicated compared to finFETs. It’s quite close. It’s 3D design. We have seen good results at 5nm. We have used nanowire to demonstrate the first silicon quantum bits. It’s based on silicon nanowire, fully compatible with CMOS processes on 300mm. Leti is going this way to address the HPC road map to push the performance as far as we can.

Van den hove: In general, if you want to continue this complexity, and , it’s clear that the amount of R&D is going to increase. You need to increase the R&D, because the problems are getting more difficult. And that’s one of the reasons why there has been the trend towards consolidation. Only the bigger companies can afford to make those transitions to the more complex technologies…There is consolidation and fewer companies will be able to do it. But the volumes are not going to decrease. The volumes in the industry are increasing. I am pretty sure that the demand will originate from the IoT. The amount of data storage that is required is mind boggling. The transition we are seeing from hard drives to solid-state drives is going to create an enormous demand for silicon, which in fact nobody will be able to supply quickly enough. So I am not so worried about the demand side. There is going to be demand.

Hansen: The basic problem, as everyone knows now and has been recognized and accepted, is that Moore’s scaling is coming to an end. The move from one technology node to next technology is taking longer. It costs more from a development perspective. The patterning that’s required is becoming more and more complex, adding process steps. The devices have gone to finFETs, which makes them more complex and requires more masks. The cost per transistor, depending on who you believe, is going up, staying flat or maybe moving slightly down. More money is going to be required to move at the pace that we’ve moved in the past.

SE: How does advanced packaging fit into this picture?

Semeria: That’s another way. You can go with 2.5D and 3D. We introduced the CoolCube, which is monolithic 3D integration. We believe that it can be very effective in lowering the cost of silicon stacking using the same process. This could be relevant for heterogeneous integration of different functions—an analog function stacked on a digital function with a high density interconnect…We optimized a low-temperature process. We developed that with Applied Materials for low-temperature epitaxy. And we developed a strategy for implantation to achieve the same rate for the top transistor as the bottom transistor. We achieved 95% of the performance of the reference transistors. Those are very recent results using CMOS as the top and bottom layers…But we are just at the beginning. We demonstrated CMOS on CMOS, pMOS on nMOS, nMOS on pMOS. We can test and demonstrate more, but the goal was to show that you can use CoolCube in a product. We have companies interested in assessing this technology… 2.5D is very flexible and efficient integration scheme. We use a 3D network on chip, which is very flexible, based on an interposer. You can mix up the technology and optimize on cost, performance, and engines.

Van den hove: If you talk about geometry-based scaling, we are not going to stay on a two-year cadence. It’s going to slow down. We will compensate that slowdown by moving into the third dimension. We are going to stay on Moore’s Law. But it won’t all come from geometry scaling. To go from one node to the next, it may take more time. But at some point in the roadmap, maybe we’ll have two transistors on top of each other. So we don’t gain that much by geometry scaling, but we gain by stacking. The net effect is that we stay on the complexity curve. But on the geometry scaling curve, it will take more time than every two years. The gains will be slower.

Hansen: There is a unique package approach born every day. Fan-out packaging, in general, is an explosive area. The only thing that’s holding back fan-out, which is just another form of SIP packaging, has always been cost.

SE: What else are you seeing?

Semeria: We have done comparisons between FD-SOI, finFETs and nanowire at 10nm, 7nm and 5nm. At 5nm nanowires are better compared to FD-SOI and finFETs in terms of electrostatic control. And you can stack the nanowires to reach higher currents, so you can have performance. We will push nanowire to one more node.

Van den hove: There is incremental progress needed on all fronts. Metrology is certainly an important area, especially as we evolve to 3D structures. The metrology gets more challenging. In deposition, a lot of progress has been made. This is driven by NAND technology, particularly vertical NAND. Etching is the same thing. I don’t see any showstoppers. We do need precision in many of those process steps at the atomic level.

Hansen: We’ve eliminated some [transistor candidates at 3nm and beyond]. Of all the categories, the magneto-electric ones seem to have the highest potential. But that’s speculative at this point. What we’re basically looking for, and we’ve seen through the course of time, is that if you find a device that will perform comparably to what we can get out of a device today, but will operate at magnitude of lower power, then you can have a net gain in terms of performance per unit of DC power consumption. It will be something that has a significantly lower power at comparable performance of today’s devices. That will be probably easy to integrate with a silicon technology.

SE: As we move into the IoT era, what changes?

Semeria: It depends on the application. To keep the low-voltage advantage of FD-SOI, we prefer PCRAM (phase-change memory) or OxRAM (oxide-based RAM). FinFETs will be required to address the high-end market. FD-SOI will be for IoT, especially for automotive, because it shows hardness against radiation. That’s a key advantage for automotive applications. We try to put more and more function in FD-SOI. So it has to be compatible with RF. FinFET isn’t so compatible with RF.

Van den hove: One of the trends is that we see more collaboration along the value chain. We see more of the fabless companies, and even systems companies and OEMs, being involved in the R&D part. They have to drive the R&D as we are deviating from this one dimensional roadmap.

Hansen: Power consumption. The other side is security. As you roll out this IoT network, which people talk in terms of 50 billion devices by 2020, you’ve increased your attack zone for hackers. The security you put at the edge cannot be anywhere near what it is at the server level.

SE: What other changes are you looking at in the future?

Semeria: We have to contemplate different architectures for computing. There is Von Neumann, of course, which is compatible with consumer architectures. For massively parallel issues, there is neuromorphic for pattern recognition…Quantum will not be the best solution for everything. We will have to combine different architectures to maximize our computing capabilities.

Van den hove: I strongly believe that we will see EUV entering the manufacturing ramp very quickly. The progress that has been made over the last 12 months is phenomenal in terms of the power and reliability of the machines, as well as resist and pellicle development. And so, it’s not a matter of whether it will happen. It’s just a matter of when it will happen, and how many of the foundries will commit to EUV at 7nm. Or will they wait to 5nm. Or will they start with a version of 7nm and then have a second version with EUV at 7nm. Those are the scenarios on the table now.

Hansen: We don’t think there is any question that you have to have material changes to be able to continue to improve device technology. We believe you need to look at co-optimization across the design hierarchy layers.

Related Stories
What Transistors Will Look Like At 5nm
As finFETs run out of steam after 7nm, what comes next? The debate is just beginning.
Will 5nm Happen?
Investments in finFET technology are hard to discard, but technical and financial challenges for getting there are huge.
5nm Fab Challenges
New transistor types, plus issues with masks, patterning, materials, process control and interconnects, add up to a very tough transition.


memister says:

Still, it’s no pellicle, no EUV.

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