tag: FD-SOI

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
By Technical Paper Link - 25 Apr, 2022 - Comments: 0

New research paper from University of Saskatchewan, with funding by NSERC and the Cisco University Research Program. Abstract "Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should be explor... » read more

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
By Technical Paper Link - 31 Aug, 2021 - Comments: 0

Abstract: "This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide�... » read more

Behind The Intel-GlobalFoundries Rumor
By Ed Sperling - 19 Jul, 2021 - Comments: 5

A Wall Street Journal report that Intel is looking to buy GlobalFoundries has sparked discussions across the industry. But what exactly this would mean, and why now versus a couple years ago, needs some context. There are layers upon layers of irony behind this would-be deal, and it dates back decades to some rather famous encounters. Consider former AMD CEO Jerry Sanders' 1991 comment that ... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Power Optimization: What’s Next?
By Brian Bailey - 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

Chip Board Interaction Analysis Of 22nm FD-SOI Technology In WLP
By Amkor - 17 Mar, 2021 - Comments: 0

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applicatio... » read more

Dealing With Sub-Threshold Variation
By Bryon Moyer - 12 Nov, 2020 - Comments: 0

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 25 Sep, 2020 - Comments: 0

Top stories Here's the latest from Reuters: ''The United States has imposed restrictions on exports to China’s biggest chip maker SMIC after concluding there is an 'unacceptable risk' equipment supplied to it could be used for military purposes." What does this all mean? “The press has reported that on Friday, the U.S. Department of Commerce placed restrictions on China's largest semicondu... » read more

Rethinking Competitive One Upmanship Among Foundries
By Ed Sperling - 03 Aug, 2020 - Comments: 2

The winner in the foundry business used to be determined by who got to the most advanced process node first. For the most part that benchmark no longer works. Unlike in the past, when all of the foundries and IDMs competed using basically the same process, each foundry has gone its own route. This is primarily due to the divergence of end markets, and the realization that as costs increase, ... » read more

Going On the Edge
By Mark LaPedus - 27 Jan, 2020 - Comments: 3

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to talk about artificial intelligence (AI), edge computing and chip technologies. What follows are excerpts of that conversation. SE: Where is AI going in the future? Sabonnadière: I am a strong believer that edge AI will change our lives. Today’s microelectronics are organized with 80% of things i... » read more

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