Rethinking Competitive One Upmanship Among Foundries

Just because features are smaller doesn’t make them more attractive.


The winner in the foundry business used to be determined by who got to the most advanced process node first. For the most part that benchmark no longer works.

Unlike in the past, when all of the foundries and IDMs competed using basically the same process, each foundry has gone its own route. This is primarily due to the divergence of end markets, and the realization that as costs increase, only a handful of companies would be able to afford or need the most advanced nodes. And while performance and power are still critical elements of a design, there are multiple ways to get there.

This shift is less about being able to develop chips at the most advanced process geometry and more about getting a competitive solution — meaning fully or semi-customized — to market as quickly as possible. For most applications, this depends upon architectures, partitioning according to function and the priorities of a particular market segment. And in most cases, it has to be profitable even in smaller volumes. Density still matters, but that density may be a combination of accelerators and other chips in an advanced package.

One by one, foundries have struggled to explain this because the answer is as diffuse as the customer base. GlobalFoundries’ decision to postpone its move to 7nm and instead concentrate on 14nm finFETs and FD-SOI was viewed as a sign of weakness. UMC decided not to push past 14nm, as well. Both UMC and GlobalFoundries are reporting strong growth..

Samsung and TSMC have made it to 7nm — roughly the equivalent of Intel’s 10nm — and both are now actively pushing to 5nm and 3nm. But logic density will only carry a design so far. The general consensus is that shrinking to 5nm and 3nm only will provide power/performance improvements of about 15% to 20%, while targeting specific functions through architecture and hardware-software co-design can boost performance by up three orders of magnitude at the same power.

This is why Intel’s focus on interconnects over the past few years, both on-chip (purchase of NetSpeed Systems) and off-chip (CXL and EMIB), is a big deal. The company is using internally sourced chiplets to customize solutions for customers, which also is a big deal. So far, only large IDMs, such as Intel, AMD and Marvell have successfully used chiplets to offer a menu of possible configurations, and of the three, only Intel still has its own fab.

That’s not the only winning approach. UMC’s focus on automotive certification will be a huge advantage once the auto market begins ramping up again. And GlobalFoundries’ focus on FD-SOI offers a planar (and potentially a packaged) alternative to bulk CMOS, which can go a long way in providing unique solutions at a lower price point for edge and IoT devices. The big wild card here is SMIC, which is pushing a whole bunch of different options for an increasingly insular supply chain.

The foundry business has changed significantly, and so have the metrics for success. Rather than a competitive race where every foundry is competing for the same prize, the manufacturing world is splintering into very distinct markets. And with smart phones growth flat, and few devices that can generate enough volume to warrant developing SoCs at the latest node (big cloud companies such as AWS, Google and Alibaba are the exception, because they can amortize the chip cost across systems of systems), this makes a lot of sense from both a business and a power/performance standpoint. There is no grand prize anymore for being the first to shrink features. The end markets are heading for mass customization, even in the cloud, and the foundries are following the various growth vectors.

So while Moore’s Law may continue in theory, it certainly doesn’t look anything like the original premise of doubling the number of transistors on a piece of silicon every 18 or 24 months. The economics are in customized solutions where datapaths and power delivery networks are unimpeded, and where those functions that define a solution are given top priority. Being first out the door with a solution for those individual markets is where the money is, and that will have a big impact on how the foundry business continues to evolve.


Dr. Dev Gupta says:

As we have discussed in the Packaging Integration section of the latest version of IEEE Semiconductor Devices Roadmap, the only way to offer alternatives to the current nexus between the large Systems / Fabless design Co.s and the large Foundry they have helped grow to near Monopoly stature is to gain a large no. of new customers by “small lot Customization” of Processor – Memory modules by integrating Chiplets using Adv. Packaging then back up the hardware with almost free modularized application software.

There is only one semiconductor Co. left that has the technology & resources to pull it off. Unfortunately it has been run down by its Board of Directors dominated by Finance types. that Board has been picking Finance people as CEOs and running to ground the pioneer of semiconductor industry, founded over 50 years ago by 3 PhDs in Sciences & Engr. ( incl. one Nobel Laureate ).

For this still powerful Co. to survive and thrive the current Board of Directors MUST BE FLUSHED OUT and replaced by hardcore experts in future applications, algorithms as well as Semiconductor tech who will then appoint CEOs with proven technology Macho and in turn boost the job satisfaction, morale, aggressiveness of the huge Engr, staff attenuated by having to support legacy moneymaking products rather than bold innovations, as well as be able to once again attract a fresh crop of PhDs from the best schools.

SomeDude says:

What happens in ten years when only two companies have a sub 1nm node and the rest are on 10nm.

Packaging is important, but it can’t replace density improvements.

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