tag: CXL

Options Grow For Standardizing Data Movement And Sharing Resources
By Ed Sperling - 20 May, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Boosting Memory Bandwidth Availability By Salvaging Idle I/O Bandwidth Resources (Georgia Tech)
By Technical Paper Link - 03 Dec, 2025 - Comments: 0

A new technical paper titled "Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting" was published by researchers at Georgia Institute of Technology. Abstract "The continual increase of cores on server-grade CPUs raises demands on memory systems, which are constrained by limited off-chip pin and data transfer rate scalability. As a result, high-end processors ty... » read more

Boosting AI Performance With CXL
By Vanessa Do - 25 Sep, 2025 - Comments: 0

As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions – or even trillions – of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training. Hence, there is a constant demand for flexible memory expansion and memory sharing among d... » read more

An Overview Of CXL Mode Alternate Protocol Negotiation
By Guo Yu - 28 Aug, 2025 - Comments: 0

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers. One of the most common alternate protocols is th... » read more

Boosting AI Performance With CXL
By Vanessa Do - 29 May, 2025 - Comments: 0

As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions – or even trillions – of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training. Hence, there is a constant demand for flexible memory expansion and memory sharing among d... » read more

Controlled Shared Memory For Dynamically Controlling Data Communication Via Shared Memory Approaches (ASU, Intel)
By Technical Paper Link - 27 Apr, 2025 - Comments: 0

A new technical paper titled "Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation" was published by researchers at Arizona State University and Intel Corporation. Abstract "Recent memory sharing approaches, e.g., based on the Compute Express Link (CXL) standard, allow the flexible high-speed sharing of data (i.e., data communication) among multiple hosts. In information... » read more

Research Bits: Apr. 1
By Jesse Allen - 01 Apr, 2025 - Comments: 0

Neuro-synaptic RAM Researchers from the National University of Singapore (NUS) and King Abdullah University of Science and Technology (KAUST) found that a standard silicon transistor can function like a biological neuron and synapse when arranged and operated in a specific way. The team was able to replicate both neural firing and synaptic weight changes by adjusting the resistance of the b... » read more

Optimizing Data Center TCO With CXL And Compression
By Raj Uppala - 13 Feb, 2025 - Comments: 0

In the ever-evolving landscape of data centers, Total Cost of Ownership (TCO) remains a critical metric. It encompasses all costs associated with data center infrastructure throughout its lifecycle, including initial purchase, installation, utilization, maintenance, energy consumption, and eventual replacement. By understanding and optimizing TCO, hyperscalers can make informed decisions that e... » read more

Topology And Connection Architecture Of CXL Pooling Systems (Microsoft, Columbia)
By Technical Paper Link - 29 Jan, 2025 - Comments: 0

A new technical paper titled "Octopus: Scalable Low-Cost CXL Memory Pooling" was published by researchers at University of Washington, Microsoft Azure and Columbia University. Abstract "Compute Express Link (CXL) is widely-supported interconnect standard that promises to enable memory disaggregation in data centers. CXL allows for memory pooling, which can be used to create a shared memory ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy