What happens to chip board interaction (CBI) during a drop test and temperature cycle on board test when testing a 22-nm FD-SOI technology platform and WLP technology. How does silicon die thickness and ball grid array (BGA) metallurgy affect results?
Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applications. However, to date its application space has been limited to a small die form factor due to challenging chip board interaction (CBI) control. The combination of ultralow dielectric constant (ULK) based advanced silicon technology and WLP is another challenge for industry to overcome.
In this article, to systematically address the CBI, a large test vehicle based on 22-nm fully depleted silicon on insulator (FD-SOI) technology platform and WLP technology is described. In particular, CBI during drop test and temperature cycle on board is investigated and its failure mode analysis is discussed. The impact of silicon die thickness and ball grid array (BGA) metallurgy is also explored.
Key words: Wafer Level Packaging (WLP), Redistribution
layer (RDL), Chip Board Interaction (CBI), Drop test,
Temperature Cycle on Board (TCoB) test
Authors:
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